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Simon Dardis
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[mips] Guard indirect and tailcall pseudo instructions correctly.
Previously these pseudo instructions were not guarded by ISA, so their select was dependant on the ordering of the entries in the DAG matcher. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39723 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317681 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/Mips/MicroMips32r6InstrInfo.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1883,3 +1883,10 @@ let AddedComplexity = 41 in {
18831883
}
18841884

18851885
def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1886+
1887+
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1888+
(TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1889+
1890+
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1891+
(TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1892+

‎lib/Target/Mips/MicroMipsInstrInfo.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,13 +1062,13 @@ let Predicates = [InMicroMips] in {
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(LW_MM addr:$addr)>;
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def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
10641064
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
1065-
1066-
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1067-
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
1068-
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1069-
(TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6;
10701065
}
10711066

1067+
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1068+
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1069+
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1070+
(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1071+
10721072
let AddedComplexity = 40 in {
10731073
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
10741074
(LH_MM addrRegImm:$a)>;

‎lib/Target/Mips/MipsInstrInfo.td

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,8 @@ def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
212212
AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
213213
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
215+
def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">,
216+
AssemblerPredicate<"!FeatureMips16">;
215217
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
216218
AssemblerPredicate<"FeatureCnMips">;
217219
def NotCnMips : Predicate<"!Subtarget->hasCnMips()">,
@@ -1544,7 +1546,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
15441546
PseudoInstExpansion<(JumpInst Opnd:$target)>;
15451547

15461548
class TailCallReg<RegisterOperand RO> :
1547-
MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
1549+
PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
15481550
}
15491551

15501552
class BAL_BR_Pseudo<Instruction RealInst> :
@@ -2087,7 +2089,7 @@ def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
20872089
BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
20882090
def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
20892091

2090-
let Predicates = [NotInMicroMips] in {
2092+
let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
20912093
def TAILCALL : TailCall<J, jmptarget>;
20922094
}
20932095

@@ -2104,6 +2106,7 @@ class PseudoIndirectBranchBase<RegisterOperand RO> :
21042106
let isBranch = 1;
21052107
let isIndirectBranch = 1;
21062108
bit isCTI = 1;
2109+
let Predicates = [NotInMips16Mode];
21072110
}
21082111

21092112
def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
@@ -2777,10 +2780,12 @@ def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
27772780
// (JALR GPR32:$dst)>;
27782781

27792782
// Tail call
2780-
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
2781-
(TAILCALL tglobaladdr:$dst)>;
2782-
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
2783-
(TAILCALL texternalsym:$dst)>;
2783+
let AdditionalPredicates = [NotInMicroMips] in {
2784+
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
2785+
(TAILCALL tglobaladdr:$dst)>;
2786+
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
2787+
(TAILCALL texternalsym:$dst)>;
2788+
}
27842789
// hi/lo relocs
27852790
multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
27862791
Register ZeroReg, RegisterOperand GPROpnd> {

‎test/CodeGen/Mips/brind-tailcall.ll

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
2+
; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC %s
3+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
4+
; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC %s
5+
; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
6+
; RUN: -relocation-model=pic < %s 2>&1 | FileCheck --check-prefix=PIC64 %s
7+
; RUN: llc -march=mips64 -debug-only=isel -mips-tail-calls=1 \
8+
; RUN: -relocation-model=static < %s 2>&1 | FileCheck --check-prefix=STATIC64 %s
9+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
10+
; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
11+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
12+
; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
13+
; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
14+
; RUN: -relocation-model=pic -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=PIC %s
15+
; RUN: llc -march=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
16+
; RUN: -relocation-model=static -mattr=+micromips < %s 2>&1 | FileCheck --check-prefix=STATIC-MM %s
17+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
18+
; RUN: -relocation-model=pic -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
19+
; RUN: llc -march=mips -debug-only=isel -mips-tail-calls=1 \
20+
; RUN: -relocation-model=static -mattr=+mips16 < %s 2>&1 | FileCheck --check-prefix=MIPS16 %s
21+
22+
; REQUIRES: asserts
23+
24+
; Test that the correct pseudo instructions are generated for indirect
25+
; branches and tail calls. Previously, the order of the DAG matcher table
26+
; determined if the correct instruction was selected for mips16.
27+
28+
declare protected void @a()
29+
30+
define void @test1(i32 %a) {
31+
entry:
32+
%0 = trunc i32 %a to i1
33+
%1 = select i1 %0,
34+
i8* blockaddress(@test1, %bb),
35+
i8* blockaddress(@test1, %bb6)
36+
indirectbr i8* %1, [label %bb, label %bb6]
37+
38+
; STATIC: PseudoIndirectBranch
39+
; STATIC-MM: PseudoIndirectBranch
40+
; STATIC-NOT: PseudoIndirectBranch64
41+
; STATIC64: PseudoIndirectBranch64
42+
; PIC: PseudoIndirectBranch
43+
; PIC-NOT: PseudoIndirectBranch64
44+
; PIC64: PseudoIndirectBranch64
45+
; MIPS16: JrcRx16
46+
bb:
47+
ret void
48+
49+
bb6:
50+
tail call void @a()
51+
52+
; STATIC: TAILCALL
53+
; STATIC-NOT: TAILCALL_MM
54+
; STATIC-MM: TAILCALL_MM
55+
; PIC: TAILCALLREG
56+
; PIC-NOT: TAILCALLREG64
57+
; PIC64: TAILCALLREG64
58+
; MIPS16: RetRA16
59+
ret void
60+
}

‎test/CodeGen/Mips/tailcall/tailcall.ll

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
; RUN: llc -march=mipsel -relocation-model=pic -mcpu=mips32r6 -mattr=+micromips \
2828
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
2929
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
30-
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
30+
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6
3131
; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
3232
; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
3333
; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
@@ -51,6 +51,7 @@ entry:
5151
; PIC32MM: jalr $25
5252
; PIC32R6: jalr $25
5353
; STATIC32: jal
54+
; STATIC32MMR6: jal
5455
; N64: jalr $25
5556
; N64R6: jalr $25
5657
; PIC16: jalrc
@@ -68,6 +69,7 @@ entry:
6869
; PIC32MM: jalr $25
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; PIC32R6: jalr $25
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; STATIC32: jal
72+
; STATIC32MMR6: jal
7173
; N64: jalr $25
7274
; N64R6: jalr $25
7375
; PIC16: jalrc
@@ -85,6 +87,7 @@ entry:
8587
; PIC32R6: jalr $25
8688
; PIC32MM: jalr $25
8789
; STATIC32: jal
90+
; STATIC32MMR6: jal
8891
; N64: jalr $25
8992
; N64R6: jalr $25
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; PIC16: jalrc
@@ -102,6 +105,7 @@ entry:
102105
; PIC32R6: jalr $25
103106
; PIC32MM: jalr $25
104107
; STATIC32: jal
108+
; SATATIC32MMR6: jal
105109
; PIC64: jalr $25
106110
; STATIC64: jal
107111
; N64R6: jalr $25
@@ -120,6 +124,7 @@ entry:
120124
; PIC32R6: jr $25
121125
; PIC32MM: jr
122126
; STATIC32: j
127+
; STATIC32MMR6: bc
123128
; PIC64: jr $25
124129
; STATIC64: j
125130
; PIC16: jalrc
@@ -161,6 +166,7 @@ entry:
161166
; PIC32R6: jrc $25
162167
; PIC32MM: jrc
163168
; STATIC32: j
169+
; STATIC32MMR6: bc
164170
; PIC64: jr $25
165171
; PIC64R6: jrc $25
166172
; PIC64R6MM: jr $25
@@ -178,6 +184,7 @@ entry:
178184
; PIC32R6: jalr $25
179185
; PIC32MM: jalr $25
180186
; STATIC32: jal
187+
; STATIC32MMR6: jal
181188
; PIC64: jalr $25
182189
; STATIC64: jal
183190
; PIC16: jalrc
@@ -199,6 +206,7 @@ entry:
199206
; PIC32R6: jrc $25
200207
; PIC32MM: jrc
201208
; STATIC32: j
209+
; STATIC32MMR6: bc
202210
; PIC64: jr $25
203211
; STATIC64: j
204212
; PIC64R6: jrc $25
@@ -214,6 +222,7 @@ entry:
214222
; PIC32R6: jalrc $25
215223
; PIC32MM: jalr $25
216224
; STATIC32: jal
225+
; STATIC32MMR6: jal
217226
; STATIC64: jal
218227
; PIC64: jalr $25
219228
; PIC64R6: jalrc $25
@@ -232,6 +241,7 @@ entry:
232241
; PIC32R6: jalr $25
233242
; PIC32MM: jalr $25
234243
; STATIC32: jal
244+
; STATIC32MMR6: jal
235245
; STATIC64: jal
236246
; PIC64: jalr $25
237247
; PIC64R6: jalr $25
@@ -250,6 +260,7 @@ entry:
250260
; PIC32R6: jalrc $25
251261
; PIC32MM: jalr $25
252262
; STATIC32: jal
263+
; STATIC32MMR6: jal
253264
; STATIC64: jal
254265
; PIC64: jalr $25
255266
; PIC64R6: jalrc $25
@@ -270,6 +281,7 @@ entry:
270281
; PIC32R6: jalrc $25
271282
; PIC32MM: jalr $25
272283
; STATIC32: jal
284+
; STATIC32MMR6: jal
273285
; STATIC64: jal
274286
; PIC64: jalr $25
275287
; PIC64R6: jalrc $25
@@ -290,6 +302,7 @@ entry:
290302
; PIC32R6: jalr $25
291303
; PIC32MM: jalr $25
292304
; STATIC32: jal
305+
; STATIC32MMR6: jal
293306
; STATIC64: jal
294307
; PIC64R6: jalr $25
295308
; PIC64: jalr $25

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