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1 | 1 | //@ compile-flags: -Copt-level=3 -Zmerge-functions=disabled
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2 | 2 | //@ min-llvm-version: 20
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3 | 3 | //@ only-64bit
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| 4 | +//@ revisions: LLVM20 LLVM21 |
| 5 | +//@ [LLVM21] min-llvm-version: 21 |
| 6 | +//@ [LLVM20] max-llvm-major-version: 20 |
4 | 7 |
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5 | 8 | // The `derive(PartialEq)` on enums with field-less variants compares discriminants,
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6 | 9 | // so make sure we emit that in some reasonable way.
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@@ -137,17 +140,20 @@ pub fn mid_nz32_eq_discr(a: Mid<NonZero<u32>>, b: Mid<NonZero<u32>>) -> bool {
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137 | 140 | pub fn mid_ac_eq_discr(a: Mid<AC>, b: Mid<AC>) -> bool {
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138 | 141 | // CHECK-LABEL: @mid_ac_eq_discr(
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139 | 142 |
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140 |
| - // CHECK: %[[A_REL_DISCR:.+]] = xor i8 %a, -128 |
| 143 | + // LLVM20: %[[A_REL_DISCR:.+]] = xor i8 %a, -128 |
141 | 144 | // CHECK: %[[A_IS_NICHE:.+]] = icmp slt i8 %a, 0
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142 | 145 | // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %a, -127
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143 | 146 | // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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144 |
| - // CHECK: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %[[A_REL_DISCR]], i8 1 |
| 147 | + // LLVM20: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %[[A_REL_DISCR]], i8 1 |
145 | 148 |
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146 |
| - // CHECK: %[[B_REL_DISCR:.+]] = xor i8 %b, -128 |
| 149 | + // LLVM20: %[[B_REL_DISCR:.+]] = xor i8 %b, -128 |
147 | 150 | // CHECK: %[[B_IS_NICHE:.+]] = icmp slt i8 %b, 0
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148 | 151 | // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %b, -127
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149 | 152 | // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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150 |
| - // CHECK: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %[[B_REL_DISCR]], i8 1 |
| 153 | + // LLVM20: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %[[B_REL_DISCR]], i8 1 |
| 154 | + |
| 155 | + // LLVM21: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %a, i8 -127 |
| 156 | + // LLVM21: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %b, i8 -127 |
151 | 157 |
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152 | 158 | // CHECK: %[[R:.+]] = icmp eq i8 %[[A_DISCR]], %[[B_DISCR]]
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153 | 159 | // CHECK: ret i1 %[[R]]
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