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[NFC] [PowerPC] Prepare test for FMA negate check
This patch adds a test file, covering outputs when some operands in FMA is negative.
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‎llvm/test/CodeGen/PowerPC/fma-negate.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple powerpc64le -verify-machineinstrs \
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; RUN: | FileCheck -check-prefix=VSX %s
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; RUN: llc < %s -mtriple powerpc64le -verify-machineinstrs -mattr=-vsx \
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; RUN: | FileCheck -check-prefix=NO-VSX %s
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define double @test_mul_sub_f64(double %a, double %b, double %c) {
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; VSX-LABEL: test_mul_sub_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubadp 1, 2, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_mul_sub_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 2, 3, 1
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul contract reassoc double %b, %c
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%1 = fsub contract reassoc double %a, %0
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ret double %1
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}
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define double @test_2mul_sub_f64(double %a, double %b, double %c, double %d) {
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; VSX-LABEL: test_2mul_sub_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsmuldp 0, 3, 4
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; VSX-NEXT: xsmsubadp 0, 1, 2
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; VSX-NEXT: fmr 1, 0
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_2mul_sub_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fmul 0, 3, 4
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; NO-VSX-NEXT: fmsub 1, 1, 2, 0
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul contract reassoc double %a, %b
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%1 = fmul contract reassoc double %c, %d
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%2 = fsub contract reassoc double %0, %1
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ret double %2
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}
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define double @test_neg_fma_f64(double %a, double %b, double %c) {
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; VSX-LABEL: test_neg_fma_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubadp 3, 1, 2
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; VSX-NEXT: fmr 1, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_neg_fma_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 1, 2, 3
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; NO-VSX-NEXT: blr
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entry:
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%0 = fsub contract reassoc double -0.0, %a
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%1 = call contract reassoc double @llvm.fma.f64(double %0, double %b,
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double %c)
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ret double %1
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}
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define float @test_mul_sub_f32(float %a, float %b, float %c) {
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; VSX-LABEL: test_mul_sub_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubasp 1, 2, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_mul_sub_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsubs 1, 2, 3, 1
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul contract reassoc float %b, %c
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%1 = fsub contract reassoc float %a, %0
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ret float %1
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}
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define float @test_2mul_sub_f32(float %a, float %b, float %c, float %d) {
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; VSX-LABEL: test_2mul_sub_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsmulsp 0, 3, 4
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; VSX-NEXT: xsmsubasp 0, 1, 2
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; VSX-NEXT: fmr 1, 0
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_2mul_sub_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fmuls 0, 3, 4
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; NO-VSX-NEXT: fmsubs 1, 1, 2, 0
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul contract reassoc float %a, %b
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%1 = fmul contract reassoc float %c, %d
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%2 = fsub contract reassoc float %0, %1
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ret float %2
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}
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define float @test_neg_fma_f32(float %a, float %b, float %c) {
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; VSX-LABEL: test_neg_fma_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubasp 3, 1, 2
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; VSX-NEXT: fmr 1, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_neg_fma_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsubs 1, 1, 2, 3
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; NO-VSX-NEXT: blr
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entry:
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%0 = fsub contract reassoc float -0.0, %a
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%1 = call contract reassoc float @llvm.fma.f32(float %0, float %b, float %c)
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ret float %1
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}
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define <2 x double> @test_neg_fma_v2f64(<2 x double> %a, <2 x double> %b,
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; VSX-LABEL: test_neg_fma_v2f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xvnmsubadp 36, 34, 35
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; VSX-NEXT: vmr 2, 4
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_neg_fma_v2f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 1, 3, 5
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; NO-VSX-NEXT: fnmsub 2, 2, 4, 6
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; NO-VSX-NEXT: blr
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<2 x double> %c) {
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entry:
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%0 = fsub contract reassoc <2 x double> <double -0.0, double -0.0>, %a
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%1 = call contract reassoc <2 x double> @llvm.fma.v2f64(<2 x double> %0,
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<2 x double> %b,
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<2 x double> %c)
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ret <2 x double> %1
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}
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define <4 x float> @test_neg_fma_v4f32(<4 x float> %a, <4 x float> %b,
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; VSX-LABEL: test_neg_fma_v4f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xvnmsubasp 36, 34, 35
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; VSX-NEXT: vmr 2, 4
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_neg_fma_v4f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: vspltisb 5, -1
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; NO-VSX-NEXT: vslw 5, 5, 5
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; NO-VSX-NEXT: vsubfp 2, 5, 2
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; NO-VSX-NEXT: vmaddfp 2, 2, 3, 4
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; NO-VSX-NEXT: blr
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<4 x float> %c) {
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entry:
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%0 = fsub contract reassoc <4 x float> <float -0.0, float -0.0, float -0.0,
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float -0.0>, %a
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%1 = call contract reassoc <4 x float> @llvm.fma.v4f32(<4 x float> %0,
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<4 x float> %b,
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<4 x float> %c)
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ret <4 x float> %1
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}
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define double @test_fast_mul_sub_f64(double %a, double %b, double %c) {
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; VSX-LABEL: test_fast_mul_sub_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubadp 1, 2, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_mul_sub_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 2, 3, 1
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul fast double %b, %c
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%1 = fsub fast double %a, %0
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ret double %1
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}
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define double @test_fast_2mul_sub_f64(double %a, double %b, double %c,
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; VSX-LABEL: test_fast_2mul_sub_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsmuldp 0, 3, 4
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; VSX-NEXT: xsmsubadp 0, 1, 2
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; VSX-NEXT: fmr 1, 0
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_2mul_sub_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fmul 0, 3, 4
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; NO-VSX-NEXT: fmsub 1, 1, 2, 0
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; NO-VSX-NEXT: blr
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double %d) {
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entry:
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%0 = fmul fast double %a, %b
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%1 = fmul fast double %c, %d
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%2 = fsub fast double %0, %1
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ret double %2
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}
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define double @test_fast_neg_fma_f64(double %a, double %b, double %c) {
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; VSX-LABEL: test_fast_neg_fma_f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubadp 3, 1, 2
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; VSX-NEXT: fmr 1, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_neg_fma_f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 1, 2, 3
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; NO-VSX-NEXT: blr
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entry:
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%0 = fsub fast double -0.0, %a
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%1 = call fast double @llvm.fma.f64(double %0, double %b, double %c)
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ret double %1
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}
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define float @test_fast_mul_sub_f32(float %a, float %b, float %c) {
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; VSX-LABEL: test_fast_mul_sub_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubasp 1, 2, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_mul_sub_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsubs 1, 2, 3, 1
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul fast float %b, %c
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%1 = fsub fast float %a, %0
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ret float %1
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}
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define float @test_fast_2mul_sub_f32(float %a, float %b, float %c, float %d) {
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; VSX-LABEL: test_fast_2mul_sub_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsmulsp 0, 3, 4
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; VSX-NEXT: xsmsubasp 0, 1, 2
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; VSX-NEXT: fmr 1, 0
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_2mul_sub_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fmuls 0, 3, 4
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; NO-VSX-NEXT: fmsubs 1, 1, 2, 0
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; NO-VSX-NEXT: blr
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entry:
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%0 = fmul fast float %a, %b
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%1 = fmul fast float %c, %d
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%2 = fsub fast float %0, %1
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ret float %2
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}
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define float @test_fast_neg_fma_f32(float %a, float %b, float %c) {
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; VSX-LABEL: test_fast_neg_fma_f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xsnmsubasp 3, 1, 2
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; VSX-NEXT: fmr 1, 3
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_neg_fma_f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsubs 1, 1, 2, 3
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; NO-VSX-NEXT: blr
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entry:
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%0 = fsub fast float -0.0, %a
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%1 = call fast float @llvm.fma.f32(float %0, float %b, float %c)
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ret float %1
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}
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define <2 x double> @test_fast_neg_fma_v2f64(<2 x double> %a, <2 x double> %b,
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; VSX-LABEL: test_fast_neg_fma_v2f64:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xvnmsubadp 36, 34, 35
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; VSX-NEXT: vmr 2, 4
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_neg_fma_v2f64:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: fnmsub 1, 1, 3, 5
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; NO-VSX-NEXT: fnmsub 2, 2, 4, 6
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; NO-VSX-NEXT: blr
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<2 x double> %c) {
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entry:
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%0 = fsub fast <2 x double> <double -0.0, double -0.0>, %a
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%1 = call fast <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %b,
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<2 x double> %c)
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ret <2 x double> %1
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}
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define <4 x float> @test_fast_neg_fma_v4f32(<4 x float> %a, <4 x float> %b,
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; VSX-LABEL: test_fast_neg_fma_v4f32:
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; VSX: # %bb.0: # %entry
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; VSX-NEXT: xvnmsubasp 36, 34, 35
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; VSX-NEXT: vmr 2, 4
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; VSX-NEXT: blr
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;
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; NO-VSX-LABEL: test_fast_neg_fma_v4f32:
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; NO-VSX: # %bb.0: # %entry
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; NO-VSX-NEXT: vspltisb 5, -1
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; NO-VSX-NEXT: vslw 5, 5, 5
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; NO-VSX-NEXT: vsubfp 2, 5, 2
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; NO-VSX-NEXT: vmaddfp 2, 2, 3, 4
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; NO-VSX-NEXT: blr
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<4 x float> %c) {
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entry:
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%0 = fsub fast <4 x float> <float -0.0, float -0.0, float -0.0,
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float -0.0>, %a
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%1 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %b,
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<4 x float> %c)
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ret <4 x float> %1
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}
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declare float @llvm.fma.f32(float %a, float %b, float %c)
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declare double @llvm.fma.f64(double %a, double %b, double %c)
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declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,
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<4 x float> %c)
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declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,
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<2 x double> %c)

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