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[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros
Given that some instructions generate wider result elements than their inputs, flag them as being able to generate non zeros in the false lanes. Differential Revision: https://reviews.llvm.org/D76766
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-11
lines changed

2 files changed

+195
-11
lines changed

‎llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Lines changed: 28 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -520,19 +520,44 @@ static bool isRegInClass(const MachineOperand &MO,
520520
return MO.isReg() && MO.getReg() && Class->contains(MO.getReg());
521521
}
522522

523+
// MVE 'narrowing' operate on half a lane, reading from half and writing
524+
// to half, which are referred to has the top and bottom half. The other
525+
// half retains its previous value.
526+
static bool retainsPreviousHalfElement(const MachineInstr &MI) {
527+
const MCInstrDesc &MCID = MI.getDesc();
528+
uint64_t Flags = MCID.TSFlags;
529+
return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
530+
}
531+
532+
// Some MVE instructions read from the top/bottom halves of their operand(s)
533+
// and generate a vector result with result elements that are double the
534+
// width of the input.
535+
static bool producesDoubleWidthResult(const MachineInstr &MI) {
536+
const MCInstrDesc &MCID = MI.getDesc();
537+
uint64_t Flags = MCID.TSFlags;
538+
return (Flags & ARMII::DoubleWidthResult) != 0;
539+
}
540+
523541
// Can this instruction generate a non-zero result when given only zeroed
524542
// operands? This allows us to know that, given operands with false bytes
525543
// zeroed by masked loads, that the result will also contain zeros in those
526544
// bytes.
527545
static bool canGenerateNonZeros(const MachineInstr &MI) {
546+
547+
// Check for instructions which can write into a larger element size,
548+
// possibly writing into a previous zero'd lane.
549+
if (producesDoubleWidthResult(MI))
550+
return true;
551+
528552
switch (MI.getOpcode()) {
529553
default:
530554
break;
531-
// FIXME: FP minus 0?
532-
//case ARM::MVE_VNEGf16:
533-
//case ARM::MVE_VNEGf32:
555+
// FIXME: VNEG FP and -0? I think we'll need to handle this once we allow
556+
// fp16 -> fp32 vector conversions.
557+
// Instructions that perform a NOT will generate 1s from 0s.
534558
case ARM::MVE_VMVN:
535559
case ARM::MVE_VORN:
560+
// Count leading zeros will do just that!
536561
case ARM::MVE_VCLZs8:
537562
case ARM::MVE_VCLZs16:
538563
case ARM::MVE_VCLZs32:
@@ -541,14 +566,6 @@ static bool canGenerateNonZeros(const MachineInstr &MI) {
541566
return false;
542567
}
543568

544-
// MVE 'narrowing' operate on half a lane, reading from half and writing
545-
// to half, which are referred to has the top and bottom half. The other
546-
// half retains its previous value.
547-
static bool retainsPreviousHalfElement(const MachineInstr &MI) {
548-
const MCInstrDesc &MCID = MI.getDesc();
549-
uint64_t Flags = MCID.TSFlags;
550-
return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
551-
}
552569

553570
// Look at its register uses to see if it only can only receive zeros
554571
// into its false lanes which would then produce zeros. Also check that

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,47 @@
751751
ret i32 %res
752752
}
753753

754+
define hidden i32 @illegal_vmull_non_zero(i16* %x, i16* %y, i16* %z, i32 %n) {
755+
entry:
756+
%cmp22 = icmp sgt i32 %n, 0
757+
%0 = add i32 %n, 7
758+
%1 = icmp slt i32 %n, 8
759+
%smin = select i1 %1, i32 %n, i32 8
760+
%2 = sub i32 %0, %smin
761+
%3 = lshr i32 %2, 3
762+
%4 = add nuw nsw i32 %3, 1
763+
br i1 %cmp22, label %while.body.preheader, label %while.end
764+
765+
while.body.preheader: ; preds = %entry
766+
call void @llvm.set.loop.iterations.i32(i32 %4)
767+
br label %while.body
768+
769+
while.body: ; preds = %while.body.preheader, %while.body
770+
%x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]
771+
%y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]
772+
%n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]
773+
%acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]
774+
%5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ]
775+
%tmp3 = bitcast i16* %y.addr.025 to <8 x i16>*
776+
%tmp1 = bitcast i16* %x.addr.026 to <8 x i16>*
777+
%tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)
778+
%tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
779+
%tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
780+
%mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)
781+
%reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul)
782+
%acc.next = add i32 %reduce, %acc
783+
%add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
784+
%add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
785+
%sub = add nsw i32 %n.addr.023, -8
786+
%6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
787+
%7 = icmp ne i32 %6, 0
788+
br i1 %7, label %while.body, label %while.end
789+
790+
while.end: ; preds = %while.body, %entry
791+
%res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]
792+
ret i32 %res
793+
}
794+
754795
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
755796
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
756797
declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
@@ -3009,3 +3050,129 @@ body: |
30093050
tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
30103051
30113052
...
3053+
---
3054+
name: illegal_vmull_non_zero
3055+
alignment: 2
3056+
tracksRegLiveness: true
3057+
registers: []
3058+
liveins:
3059+
- { reg: '$r0', virtual-reg: '' }
3060+
- { reg: '$r1', virtual-reg: '' }
3061+
- { reg: '$r3', virtual-reg: '' }
3062+
frameInfo:
3063+
stackSize: 8
3064+
offsetAdjustment: 0
3065+
maxAlignment: 4
3066+
fixedStack: []
3067+
stack:
3068+
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
3069+
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
3070+
debug-info-variable: '', debug-info-expression: '', debug-info-___location: '' }
3071+
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
3072+
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
3073+
debug-info-variable: '', debug-info-expression: '', debug-info-___location: '' }
3074+
callSites: []
3075+
constants: []
3076+
machineFunctionInfo: {}
3077+
body: |
3078+
; CHECK-LABEL: name: illegal_vmull_non_zero
3079+
; CHECK: bb.0.entry:
3080+
; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000)
3081+
; CHECK: liveins: $lr, $r0, $r1, $r3, $r7
3082+
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
3083+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
3084+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
3085+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
3086+
; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
3087+
; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
3088+
; CHECK: t2IT 10, 8, implicit-def $itstate
3089+
; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
3090+
; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
3091+
; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
3092+
; CHECK: bb.1.while.body.preheader:
3093+
; CHECK: successors: %bb.2(0x80000000)
3094+
; CHECK: liveins: $r0, $r1, $r2, $r3
3095+
; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
3096+
; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
3097+
; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
3098+
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
3099+
; CHECK: dead $lr = t2DLS renamable $r2
3100+
; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3101+
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
3102+
; CHECK: bb.2.while.body:
3103+
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
3104+
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
3105+
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
3106+
; CHECK: MVE_VPST 4, implicit $vpr
3107+
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
3108+
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
3109+
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
3110+
; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
3111+
; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
3112+
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
3113+
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
3114+
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
3115+
; CHECK: bb.3.while.end:
3116+
; CHECK: liveins: $r2
3117+
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3118+
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
3119+
; CHECK: bb.4:
3120+
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
3121+
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3122+
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
3123+
bb.0.entry:
3124+
successors: %bb.1(0x50000000), %bb.4(0x30000000)
3125+
liveins: $r0, $r1, $r3, $r7, $lr
3126+
3127+
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
3128+
frame-setup CFI_INSTRUCTION def_cfa_offset 8
3129+
frame-setup CFI_INSTRUCTION offset $lr, -4
3130+
frame-setup CFI_INSTRUCTION offset $r7, -8
3131+
tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
3132+
$r2 = tMOVr $r3, 14 /* CC::al */, $noreg
3133+
t2IT 10, 8, implicit-def $itstate
3134+
renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
3135+
tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
3136+
tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
3137+
3138+
bb.1.while.body.preheader:
3139+
successors: %bb.2(0x80000000)
3140+
liveins: $r0, $r1, $r2, $r3
3141+
3142+
renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
3143+
renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
3144+
renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
3145+
renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
3146+
t2DoLoopStart renamable $r2
3147+
$r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3148+
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
3149+
3150+
bb.2.while.body:
3151+
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
3152+
liveins: $r0, $r1, $r2, $r3, $r12
3153+
3154+
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
3155+
MVE_VPST 4, implicit $vpr
3156+
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
3157+
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
3158+
$lr = tMOVr $r12, 14 /* CC::al */, $noreg
3159+
renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
3160+
renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
3161+
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
3162+
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
3163+
renamable $lr = t2LoopDec killed renamable $lr, 1
3164+
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
3165+
tB %bb.3, 14 /* CC::al */, $noreg
3166+
3167+
bb.3.while.end:
3168+
liveins: $r2
3169+
3170+
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3171+
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
3172+
3173+
bb.4:
3174+
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
3175+
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
3176+
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
3177+
3178+
...

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