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e1000: setup interrupts
Signed-off-by: Andy-Python-Programmer <[email protected]>
1 parent d7bc6a9 commit 7c1a1b9

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4 files changed

+80
-6
lines changed

4 files changed

+80
-6
lines changed

src/aero_kernel/src/acpi/aml.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ pub trait AmlSubsystem: Send + Sync {
1717
/// ## Parameters
1818
/// * `mode` - IRQ mode (ACPI spec section 5.8.1)
1919
fn enable_acpi(&self, mode: u32);
20+
fn pci_route_pin(&self, seg: u16, bus: u8, slot: u8, function: u8, pin: u8) -> u8;
2021
}
2122

2223
static AML_SUBSYSTEM: Once<Arc<dyn AmlSubsystem>> = Once::new();

src/aero_kernel/src/drivers/e1000.rs

Lines changed: 62 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@
1919

2020
use alloc::sync::Arc;
2121

22+
use crate::acpi::aml;
23+
use crate::arch::interrupts::{self, InterruptStack};
2224
use crate::drivers::pci::*;
2325
use crate::mem::paging::*;
2426

@@ -39,10 +41,15 @@ enum Error {
3941
#[derive(Copy, Clone)]
4042
#[repr(usize)]
4143
enum Register {
42-
Control = 0x00,
44+
Control = 0x0,
45+
Status = 0x8,
46+
4347
Eeprom = 0x14,
4448

45-
RCtrl = 0x0100,
49+
ICause = 0xc0,
50+
IMask = 0xd0,
51+
52+
RCtrl = 0x100,
4653
/// Lower bits of the 64 bit descriptor base address.
4754
RxDescLo = 0x2800,
4855
/// Upper 32 bits of the 64 bit descriptor base address.
@@ -90,6 +97,18 @@ bitflags::bitflags! {
9097
}
9198
}
9299

100+
bitflags::bitflags! {
101+
struct ECtl: u32 {
102+
const LRST = (1 << 3);
103+
const ASDE = (1 << 5);
104+
const SLU = (1 << 6); // Set Link Up
105+
const ILOS = (1 << 7);
106+
const RST = (1 << 26);
107+
const VME = (1 << 30);
108+
const PHY_RST = (1 << 31);
109+
}
110+
}
111+
93112
bitflags::bitflags! {
94113
struct TCtl: u32 {
95114
const EN = 1 << 1; // Transmit Enable
@@ -208,6 +227,11 @@ impl E1000 {
208227
_ => return Err(Error::UnknownBar),
209228
};
210229

230+
log::debug!(
231+
"{:?}",
232+
header.capabilities().collect::<alloc::vec::Vec<_>>()
233+
);
234+
211235
let this = Self {
212236
base: registers_addr.as_hhdm_virt(),
213237
};
@@ -242,10 +266,42 @@ impl E1000 {
242266
this.init_tx()?;
243267
this.init_rx()?;
244268

269+
// XXX: The e1000 does not support MSIx and MSI.
270+
let gsi = aml::get_subsystem().pci_route_pin(
271+
0,
272+
header.bus(),
273+
header.device(),
274+
header.function(),
275+
header.interrupt_pin(),
276+
);
277+
278+
let vector = interrupts::allocate_vector();
279+
interrupts::register_handler(vector, irq_handler);
280+
281+
crate::arch::apic::io_apic_setup_legacy_irq(gsi, vector, 0);
282+
283+
// Enable interrupts!
284+
this.write(Register::IMask, 0);
285+
this.read(Register::ICause);
286+
287+
this.link_up();
288+
289+
this.receive();
290+
245291
log::trace!("e1000: successfully initialized");
246292
Ok(())
247293
}
248294

295+
fn receive(&self) {}
296+
297+
fn link_up(&self) {
298+
self.insert_flags(Register::Control, ECtl::SLU.bits());
299+
300+
while self.read(Register::Status) & 2 != 2 {
301+
core::hint::spin_loop();
302+
}
303+
}
304+
249305
fn init_tx(&self) -> Result<(), Error> {
250306
assert!(TX_DESC_SIZE < Size4KiB::SIZE as u32);
251307

@@ -395,6 +451,10 @@ impl PciDeviceHandle for Handler {
395451
}
396452
}
397453

454+
fn irq_handler(_stack: &mut InterruptStack) {
455+
unreachable!()
456+
}
457+
398458
fn init() {
399459
register_device_driver(Handler::new())
400460
}

src/aero_kernel/src/drivers/lai.rs

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,12 @@ impl aml::AmlSubsystem for LaiSubsystem {
121121
fn enable_acpi(&self, mode: u32) {
122122
lai::enable_acpi(mode);
123123
}
124+
125+
fn pci_route_pin(&self, seg: u16, bus: u8, slot: u8, function: u8, pin: u8) -> u8 {
126+
lai::pci_route_pin(seg, bus, slot, function, pin)
127+
.expect("lai: failed to route pin")
128+
.base as u8
129+
}
124130
}
125131

126132
pub fn init_lai() {
@@ -134,4 +140,4 @@ pub fn init_lai() {
134140
aml::init(subsystem);
135141
}
136142

137-
crate::module_init!(init_lai, ModuleType::Other);
143+
crate::module_init!(init_lai, ModuleType::Block);

src/aero_kernel/src/drivers/pci.rs

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -586,10 +586,13 @@ impl PciHeader {
586586

587587
io::outl(PCI_CONFIG_ADDRESS_PORT, address);
588588

589+
let offset = (offset & 0b11) * 8;
590+
let val = io::inl(PCI_CONFIG_DATA_PORT);
591+
589592
match core::mem::size_of::<T>() {
590-
1 => io::inb(PCI_CONFIG_DATA_PORT) as u32, // u8
591-
2 => io::inw(PCI_CONFIG_DATA_PORT) as u32, // u16
592-
4 => io::inl(PCI_CONFIG_DATA_PORT), // u32
593+
1 => (val >> offset) as u8 as u32, // u8
594+
2 => (val >> offset) as u16 as u32, // u16
595+
4 => val, // u32
593596
width => unreachable!("unknown PCI read width: `{}`", width),
594597
}
595598
}
@@ -730,6 +733,10 @@ impl PciHeader {
730733
}
731734
}
732735

736+
pub fn interrupt_pin(&self) -> u8 {
737+
unsafe { self.read::<u8>(0x3d) as u8 }
738+
}
739+
733740
// NOTE: The Base Address registers are optional registers used to map internal
734741
// (device-specific) registers into Memory or I/O Spaces. Refer to the PCI Local Bus
735742
// Specification for a detailed discussion of base address registers.

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