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[RISCV] Codegen support for memory operations
This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support for lowering global addresses follow in the next patch. Differential Revision: https://reviews.llvm.org/D29934 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317685 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -49,6 +49,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setStackPointerRegisterToSaveRestore(RISCV::X2);
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for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
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setLoadExtAction(N, XLenVT, MVT::i1, Promote);
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// TODO: add all necessary setOperationAction calls.
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setBooleanContents(ZeroOrOneBooleanContent);

‎lib/Target/RISCV/RISCVInstrInfo.cpp

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@@ -29,3 +29,15 @@
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using namespace llvm;
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RISCVInstrInfo::RISCVInstrInfo() : RISCVGenInstrInfo() {}
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void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg,
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unsigned SrcReg, bool KillSrc) const {
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assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
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"Impossible reg-to-reg copy");
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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}

‎lib/Target/RISCV/RISCVInstrInfo.h

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@@ -26,6 +26,10 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
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public:
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RISCVInstrInfo();
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const override;
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};
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}
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‎lib/Target/RISCV/RISCVInstrInfo.td

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@@ -311,3 +311,31 @@ def : PatGprSimm12<setult, SLTIU>;
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let isBarrier = 1, isReturn = 1, isTerminator = 1 in
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def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
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PseudoInstExpansion<(JALR X0, X1, 0)>;
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/// Loads
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multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
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def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
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def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
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(Inst GPR:$rs1, simm12:$imm12)>;
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}
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defm : LdPat<sextloadi8, LB>;
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defm : LdPat<extloadi8, LB>;
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defm : LdPat<sextloadi16, LH>;
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defm : LdPat<extloadi16, LH>;
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defm : LdPat<load, LW>;
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defm : LdPat<zextloadi8, LBU>;
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defm : LdPat<zextloadi16, LHU>;
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/// Stores
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multiclass StPat<PatFrag StoreOp, RVInst Inst> {
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def : Pat<(StoreOp GPR:$rs2, GPR:$rs1), (Inst GPR:$rs2, GPR:$rs1, 0)>;
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def : Pat<(StoreOp GPR:$rs2, (add GPR:$rs1, simm12:$imm12)),
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(Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
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}
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defm : StPat<truncstorei8, SB>;
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defm : StPat<truncstorei16, SH>;
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defm : StPat<store, SW>;

‎test/CodeGen/RISCV/mem.ll

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@@ -0,0 +1,177 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; Check indexed and unindexed, sext, zext and anyext loads
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define i32 @lb(i8 *%a) nounwind {
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; RV32I-LABEL: lb:
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; RV32I: # BB#0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lb a0, 1(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = getelementptr i8, i8* %a, i32 1
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%2 = load i8, i8* %1
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%3 = sext i8 %2 to i32
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; the unused load will produce an anyext for selection
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%4 = load volatile i8, i8* %a
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ret i32 %3
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}
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define i32 @lh(i16 *%a) nounwind {
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; RV32I-LABEL: lh:
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; RV32I: # BB#0:
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; RV32I-NEXT: lh a1, 0(a0)
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; RV32I-NEXT: lh a0, 4(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = getelementptr i16, i16* %a, i32 2
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%2 = load i16, i16* %1
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%3 = sext i16 %2 to i32
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; the unused load will produce an anyext for selection
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%4 = load volatile i16, i16* %a
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ret i32 %3
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}
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define i32 @lw(i32 *%a) nounwind {
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; RV32I-LABEL: lw:
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; RV32I: # BB#0:
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; RV32I-NEXT: lw a1, 0(a0)
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; RV32I-NEXT: lw a0, 12(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = getelementptr i32, i32* %a, i32 3
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%2 = load i32, i32* %1
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%3 = load volatile i32, i32* %a
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ret i32 %2
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}
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define i32 @lbu(i8 *%a) nounwind {
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; RV32I-LABEL: lbu:
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; RV32I: # BB#0:
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; RV32I-NEXT: lbu a1, 0(a0)
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; RV32I-NEXT: lbu a0, 4(a0)
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = getelementptr i8, i8* %a, i32 4
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%2 = load i8, i8* %1
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%3 = zext i8 %2 to i32
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%4 = load volatile i8, i8* %a
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%5 = zext i8 %4 to i32
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%6 = add i32 %3, %5
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ret i32 %6
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}
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define i32 @lhu(i16 *%a) nounwind {
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; RV32I-LABEL: lhu:
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; RV32I: # BB#0:
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; RV32I-NEXT: lhu a1, 0(a0)
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; RV32I-NEXT: lhu a0, 10(a0)
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = getelementptr i16, i16* %a, i32 5
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i32
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%4 = load volatile i16, i16* %a
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%5 = zext i16 %4 to i32
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%6 = add i32 %3, %5
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ret i32 %6
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}
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; Check indexed and unindexed stores
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define void @sb(i8 *%a, i8 %b) nounwind {
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; RV32I-LABEL: sb:
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; RV32I: # BB#0:
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; RV32I-NEXT: sb a1, 6(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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store i8 %b, i8* %a
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%1 = getelementptr i8, i8* %a, i32 6
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store i8 %b, i8* %1
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ret void
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}
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define void @sh(i16 *%a, i16 %b) nounwind {
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; RV32I-LABEL: sh:
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; RV32I: # BB#0:
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; RV32I-NEXT: sh a1, 14(a0)
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; RV32I-NEXT: sh a1, 0(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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store i16 %b, i16* %a
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%1 = getelementptr i16, i16* %a, i32 7
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store i16 %b, i16* %1
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ret void
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}
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define void @sw(i32 *%a, i32 %b) nounwind {
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; RV32I-LABEL: sw:
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; RV32I: # BB#0:
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; RV32I-NEXT: sw a1, 32(a0)
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: jalr zero, ra, 0
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store i32 %b, i32* %a
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%1 = getelementptr i32, i32* %a, i32 8
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store i32 %b, i32* %1
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ret void
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}
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; Check load and store to an i1 ___location
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define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
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; RV32I-LABEL: load_sext_zext_anyext_i1:
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; RV32I: # BB#0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a0, 2(a0)
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i32
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i32
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%7 = add i32 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i32 %7
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}
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define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
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; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
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; RV32I: # BB#0:
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; RV32I-NEXT: lb a1, 0(a0)
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a0, 2(a0)
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i16
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i16
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%7 = add i16 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i16 %7
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define i32 @lw_sw_constant(i32 %a) nounwind {
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; TODO: the addi should be folded in to the lw/sw
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; RV32I-LABEL: lw_sw_constant:
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; RV32I: # BB#0:
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; RV32I-NEXT: lui a1, 912092
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; RV32I-NEXT: addi a2, a1, -273
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; RV32I-NEXT: lw a1, 0(a2)
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; RV32I-NEXT: sw a0, 0(a2)
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; RV32I-NEXT: addi a0, a1, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = inttoptr i32 3735928559 to i32*
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%2 = load volatile i32, i32* %1
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store i32 %a, i32* %1
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ret i32 %2
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}

‎test/CodeGen/RISCV/wide-mem.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; Check load/store operations on values wider than what is natively supported
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define i64 @load_i64(i64 *%a) nounwind {
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; RV32I-LABEL: load_i64:
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; RV32I: # BB#0:
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; RV32I-NEXT: lw a2, 0(a0)
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; RV32I-NEXT: lw a1, 4(a0)
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; RV32I-NEXT: addi a0, a2, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = load i64, i64* %a
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ret i64 %1
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}

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