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[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, nhaehnle, rampitec Differential Revision: https://reviews.llvm.org/D27100 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288657 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/AMDGPU/SMInstructions.td

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -394,16 +394,24 @@ multiclass SM_Real_Loads_vi<bits<8> op, string ps,
394394
}
395395
}
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397+
class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
398+
// encoding
399+
bits<7> sdata;
400+
401+
let sdst = ?;
402+
let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
403+
}
404+
397405
multiclass SM_Real_Stores_vi<bits<8> op, string ps,
398406
SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
399407
SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
400408
// FIXME: The operand name $offset is inconsistent with $soff used
401409
// in the pseudo
402-
def _IMM_vi : SMEM_Real_vi <op, immPs> {
410+
def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
403411
let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
404412
}
405413

406-
def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
414+
def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
407415
let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
408416
}
409417
}
@@ -427,6 +435,7 @@ defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
427435
defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
428436
defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
429437

438+
// These instructions use same encoding
430439
def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
431440
def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
432441
def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;

‎test/MC/AMDGPU/smem.s

Lines changed: 36 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,66 @@
1+
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
2+
// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SICI %s
13
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
2-
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI %s
3-
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s
4+
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSICI %s
5+
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSICI %s
6+
// RUN: not llvm-mc -arch=amdgcn -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=NOSICI %s
47

58
s_dcache_wb
69
// VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
7-
// NOSI: error: instruction not supported on this GPU
10+
// NOSICI: error: instruction not supported on this GPU
811

912
s_dcache_wb_vol
1013
// VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
11-
// NOSI: error: instruction not supported on this GPU
14+
// NOSICI: error: instruction not supported on this GPU
1215

1316
s_memrealtime s[4:5]
1417
// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
15-
// NOSI: error: instruction not supported on this GPU
18+
// NOSICI: error: instruction not supported on this GPU
1619

1720
// FIXME: Should error about instruction on GPU
1821
s_store_dword s1, s[2:3], 0xfc
1922
// VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
20-
// NOSI: error: instruction not supported on this GPU
23+
// NOSICI: error: instruction not supported on this GPU
2124

2225
s_store_dword s1, s[2:3], 0xfc glc
2326
// VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
24-
// NOSI: error: invalid operand for instruction
27+
// NOSICI: error: invalid operand for instruction
2528

2629
s_store_dword s1, s[2:3], s4
2730
// VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
28-
// NOSI: error: instruction not supported on this GPU
31+
// NOSICI: error: instruction not supported on this GPU
2932

3033
s_store_dword s1, s[2:3], s4 glc
3134
// VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
32-
// NOSI: error: invalid operand for instruction
35+
// NOSICI: error: invalid operand for instruction
3336

3437
// FIXME: Should error on SI instead of silently ignoring glc
3538
s_load_dword s1, s[2:3], 0xfc glc
3639
// VI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
3740

3841
s_load_dword s1, s[2:3], s4 glc
3942
// VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
43+
44+
s_buffer_store_dword s10, s[92:95], m0
45+
// VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
46+
// NOSICI: error: instruction not supported on this GPU
47+
48+
s_buffer_store_dwordx2 s[10:11], s[92:95], m0
49+
// VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
50+
// NOSICI: error: instruction not supported on this GPU
51+
52+
s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc
53+
// VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
54+
// NOSICI: error: invalid operand for instruction
55+
56+
s_buffer_load_dword s10, s[92:95], m0
57+
// VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
58+
// SICI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0x7c,0x5c,0x05,0xc2]
59+
60+
s_buffer_load_dwordx2 s[10:11], s[92:95], m0
61+
// VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
62+
// SICI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0x7c,0x5c,0x45,0xc2]
63+
64+
// FIXME: Should error on SI instead of silently ignoring glc
65+
s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc
66+
// VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]

‎test/MC/Disassembler/AMDGPU/smem_vi.txt

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,39 @@
88

99
# VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
1010
0x00 0x01 0x94 0xc0 0x00 0x00 0x00 0x00
11+
12+
# VI: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
13+
0x41 0x00 0x42 0xc0 0xfc 0x00 0x00 0x00
14+
15+
# VI: s_store_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x43,0xc0,0xfc,0x00,0x00,0x00]
16+
0x41 0x00 0x43 0xc0 0xfc 0x00 0x00 0x00
17+
18+
# VI: s_store_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x40,0xc0,0x04,0x00,0x00,0x00]
19+
0x41 0x00 0x40 0xc0 0x04 0x00 0x00 0x00
20+
21+
# VI: s_store_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x41,0xc0,0x04,0x00,0x00,0x00]
22+
0x41 0x00 0x41 0xc0 0x04 0x00 0x00 0x00
23+
24+
# VI: s_load_dword s1, s[2:3], 0xfc glc ; encoding: [0x41,0x00,0x03,0xc0,0xfc,0x00,0x00,0x00]
25+
0x41 0x00 0x03 0xc0 0xfc 0x00 0x00 0x00
26+
27+
# VI: s_load_dword s1, s[2:3], s4 glc ; encoding: [0x41,0x00,0x01,0xc0,0x04,0x00,0x00,0x00]
28+
0x41 0x00 0x01 0xc0 0x04 0x00 0x00 0x00
29+
30+
# VI: s_buffer_store_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x60,0xc0,0x7c,0x00,0x00,0x00]
31+
0xae 0x02 0x60 0xc0 0x7c 0x00 0x00 0x00
32+
33+
# VI: s_buffer_store_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x64,0xc0,0x7c,0x00,0x00,0x00]
34+
0xae 0x02 0x64 0xc0 0x7c 0x00 0x00 0x00
35+
36+
# VI: s_buffer_store_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x69,0xc0,0x7c,0x00,0x00,0x00]
37+
0x2e 0x02 0x69 0xc0 0x7c 0x00 0x00 0x00
38+
39+
# VI: s_buffer_load_dword s10, s[92:95], m0 ; encoding: [0xae,0x02,0x20,0xc0,0x7c,0x00,0x00,0x00]
40+
0xae 0x02 0x20 0xc0 0x7c 0x00 0x00 0x00
41+
42+
# VI: s_buffer_load_dwordx2 s[10:11], s[92:95], m0 ; encoding: [0xae,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
43+
0xae 0x02 0x24 0xc0 0x7c 0x00 0x00 0x00
44+
45+
# VI: s_buffer_load_dwordx4 s[8:11], s[92:95], m0 glc ; encoding: [0x2e,0x02,0x29,0xc0,0x7c,0x00,0x00,0x00]
46+
0x2e 0x02 0x29 0xc0 0x7c 0x00 0x00 0x00

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