@@ -537,6 +537,15 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
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case MVT::f80: // No f80 support yet.
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default : return false ;
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case MVT::i1: {
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+ // In case ValReg is a K register, COPY to a GPR
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+ if (MRI.getRegClass (ValReg) == &X86::VK1RegClass) {
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+ unsigned KValReg = ValReg;
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+ ValReg = createResultReg (Subtarget->is64Bit () ? &X86::GR8RegClass
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+ : &X86::GR8_ABCD_LRegClass);
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+ BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
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+ TII.get (TargetOpcode::COPY), ValReg)
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+ .addReg (KValReg);
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+ }
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// Mask out all but lowest bit.
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unsigned AndResult = createResultReg (&X86::GR8RegClass);
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BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
@@ -1268,6 +1277,15 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
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if (SrcVT == MVT::i1) {
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if (Outs[0 ].Flags .isSExt ())
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return false ;
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+ // In case SrcReg is a K register, COPY to a GPR
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+ if (MRI.getRegClass (SrcReg) == &X86::VK1RegClass) {
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+ unsigned KSrcReg = SrcReg;
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+ SrcReg = createResultReg (Subtarget->is64Bit () ? &X86::GR8RegClass
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+ : &X86::GR8_ABCD_LRegClass);
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+ BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
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+ TII.get (TargetOpcode::COPY), SrcReg)
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+ .addReg (KSrcReg);
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+ }
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SrcReg = fastEmitZExtFromI1 (MVT::i8 , SrcReg, /* TODO: Kill=*/ false );
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SrcVT = MVT::i8 ;
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}
@@ -1559,15 +1577,14 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) {
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// Handle zero-extension from i1 to i8, which is common.
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MVT SrcVT = TLI.getSimpleValueType (DL, I->getOperand (0 )->getType ());
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if (SrcVT == MVT::i1) {
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- if (!Subtarget->is64Bit ()) {
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- // If this isn't a 64-bit target we need to constrain the reg class
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- // to avoid high registers here otherwise we might use a high register
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- // to copy from a mask register.
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- unsigned OldReg = ResultReg;
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- ResultReg = createResultReg (&X86::GR8_ABCD_LRegClass);
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+ // In case ResultReg is a K register, COPY to a GPR
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+ if (MRI.getRegClass (ResultReg) == &X86::VK1RegClass) {
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+ unsigned KResultReg = ResultReg;
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+ ResultReg = createResultReg (Subtarget->is64Bit () ? &X86::GR8RegClass
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+ : &X86::GR8_ABCD_LRegClass);
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BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
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TII.get (TargetOpcode::COPY), ResultReg)
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- .addReg (OldReg );
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+ .addReg (KResultReg );
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}
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// Set the high bits to zero.
@@ -2096,7 +2113,8 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
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// In case OpReg is a K register, COPY to a GPR
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if (MRI.getRegClass (CondReg) == &X86::VK1RegClass) {
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unsigned KCondReg = CondReg;
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- CondReg = createResultReg (&X86::GR8RegClass);
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+ CondReg = createResultReg (Subtarget->is64Bit () ?
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+ &X86::GR8RegClass : &X86::GR8_ABCD_LRegClass);
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BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
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TII.get (TargetOpcode::COPY), CondReg)
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.addReg (KCondReg, getKillRegState (CondIsKill));
@@ -2309,7 +2327,8 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
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// In case OpReg is a K register, COPY to a GPR
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if (MRI.getRegClass (CondReg) == &X86::VK1RegClass) {
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unsigned KCondReg = CondReg;
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- CondReg = createResultReg (&X86::GR8RegClass);
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+ CondReg = createResultReg (Subtarget->is64Bit () ?
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+ &X86::GR8RegClass : &X86::GR8_ABCD_LRegClass);
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BuildMI (*FuncInfo.MBB , FuncInfo.InsertPt , DbgLoc,
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TII.get (TargetOpcode::COPY), CondReg)
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.addReg (KCondReg, getKillRegState (CondIsKill));
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