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[AVX-512] Pre-emptively fix more places in fastisel where we might copy a VK1 register into a AH/BH/CH/DH register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297704 91177308-0d34-0410-b5e6-96231b3b80d8
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1 file changed

+28
-9
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lib/Target/X86/X86FastISel.cpp

Lines changed: 28 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -537,6 +537,15 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
537537
case MVT::f80: // No f80 support yet.
538538
default: return false;
539539
case MVT::i1: {
540+
// In case ValReg is a K register, COPY to a GPR
541+
if (MRI.getRegClass(ValReg) == &X86::VK1RegClass) {
542+
unsigned KValReg = ValReg;
543+
ValReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass
544+
: &X86::GR8_ABCD_LRegClass);
545+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
546+
TII.get(TargetOpcode::COPY), ValReg)
547+
.addReg(KValReg);
548+
}
540549
// Mask out all but lowest bit.
541550
unsigned AndResult = createResultReg(&X86::GR8RegClass);
542551
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
@@ -1268,6 +1277,15 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
12681277
if (SrcVT == MVT::i1) {
12691278
if (Outs[0].Flags.isSExt())
12701279
return false;
1280+
// In case SrcReg is a K register, COPY to a GPR
1281+
if (MRI.getRegClass(SrcReg) == &X86::VK1RegClass) {
1282+
unsigned KSrcReg = SrcReg;
1283+
SrcReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass
1284+
: &X86::GR8_ABCD_LRegClass);
1285+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1286+
TII.get(TargetOpcode::COPY), SrcReg)
1287+
.addReg(KSrcReg);
1288+
}
12711289
SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
12721290
SrcVT = MVT::i8;
12731291
}
@@ -1559,15 +1577,14 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) {
15591577
// Handle zero-extension from i1 to i8, which is common.
15601578
MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType());
15611579
if (SrcVT == MVT::i1) {
1562-
if (!Subtarget->is64Bit()) {
1563-
// If this isn't a 64-bit target we need to constrain the reg class
1564-
// to avoid high registers here otherwise we might use a high register
1565-
// to copy from a mask register.
1566-
unsigned OldReg = ResultReg;
1567-
ResultReg = createResultReg(&X86::GR8_ABCD_LRegClass);
1580+
// In case ResultReg is a K register, COPY to a GPR
1581+
if (MRI.getRegClass(ResultReg) == &X86::VK1RegClass) {
1582+
unsigned KResultReg = ResultReg;
1583+
ResultReg = createResultReg(Subtarget->is64Bit() ? &X86::GR8RegClass
1584+
: &X86::GR8_ABCD_LRegClass);
15681585
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
15691586
TII.get(TargetOpcode::COPY), ResultReg)
1570-
.addReg(OldReg);
1587+
.addReg(KResultReg);
15711588
}
15721589

15731590
// Set the high bits to zero.
@@ -2096,7 +2113,8 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
20962113
// In case OpReg is a K register, COPY to a GPR
20972114
if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
20982115
unsigned KCondReg = CondReg;
2099-
CondReg = createResultReg(&X86::GR8RegClass);
2116+
CondReg = createResultReg(Subtarget->is64Bit() ?
2117+
&X86::GR8RegClass : &X86::GR8_ABCD_LRegClass);
21002118
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
21012119
TII.get(TargetOpcode::COPY), CondReg)
21022120
.addReg(KCondReg, getKillRegState(CondIsKill));
@@ -2309,7 +2327,8 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
23092327
// In case OpReg is a K register, COPY to a GPR
23102328
if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
23112329
unsigned KCondReg = CondReg;
2312-
CondReg = createResultReg(&X86::GR8RegClass);
2330+
CondReg = createResultReg(Subtarget->is64Bit() ?
2331+
&X86::GR8RegClass : &X86::GR8_ABCD_LRegClass);
23132332
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
23142333
TII.get(TargetOpcode::COPY), CondReg)
23152334
.addReg(KCondReg, getKillRegState(CondIsKill));

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