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fix: regression
1 parent a312799 commit 003f1ee

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2 files changed

+16
-10
lines changed

2 files changed

+16
-10
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3929,10 +3929,19 @@ SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N, const SDLoc &DL) {
39293929
// trunc (ABDU/S A, B)) → ABDU/S (trunc A), (trunc B)
39303930
SDValue DAGCombiner::foldAbdToNarrowType(EVT VT, SDNode *N, const SDLoc &DL) {
39313931
SDValue Op = N->getOperand(0);
3932+
39323933
unsigned Opcode = Op.getOpcode();
39333934
if (Opcode != ISD::ABDU && Opcode != ISD::ABDS)
39343935
return SDValue();
39353936

3937+
SDValue Operand0 = Op.getOperand(0);
3938+
SDValue Operand1 = Op.getOperand(1);
3939+
3940+
// Early exit if either operand is zero.
3941+
if (ISD::isBuildVectorAllZeros(Operand0.getNode()) ||
3942+
ISD::isBuildVectorAllZeros(Operand1.getNode()))
3943+
return SDValue();
3944+
39363945
EVT SrcVT = Op.getValueType();
39373946
EVT TruncVT = N->getValueType(0);
39383947
unsigned NumSrcBits = SrcVT.getScalarSizeInBits();
@@ -3950,8 +3959,8 @@ SDValue DAGCombiner::foldAbdToNarrowType(EVT VT, SDNode *N, const SDLoc &DL) {
39503959
}
39513960

39523961
if (CanFold) {
3953-
SDValue NewOp0 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Op.getOperand(0));
3954-
SDValue NewOp1 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Op.getOperand(1));
3962+
SDValue NewOp0 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Operand0);
3963+
SDValue NewOp1 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Operand1);
39553964
return DAG.getNode(Opcode, DL, TruncVT, NewOp0, NewOp1);
39563965
}
39573966

llvm/test/CodeGen/AArch64/abd-combine.ll

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,6 @@ define <8 x i16> @abdu_const_lhs(<8 x i16> %src1) {
4545
define <8 x i16> @abdu_const_zero(<8 x i16> %src1) {
4646
; CHECK-LABEL: abdu_const_zero:
4747
; CHECK: // %bb.0:
48-
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
49-
; CHECK-NEXT: abs v0.4h, v0.4h
50-
; CHECK-NEXT: abs v1.4h, v1.4h
51-
; CHECK-NEXT: mov v0.d[1], v1.d[0]
5248
; CHECK-NEXT: ret
5349
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
5450
%sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1
@@ -344,10 +340,11 @@ define <8 x i16> @abds_const_lhs(<8 x i16> %src1) {
344340
define <8 x i16> @abds_const_zero(<8 x i16> %src1) {
345341
; CHECK-LABEL: abds_const_zero:
346342
; CHECK: // %bb.0:
347-
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
348-
; CHECK-NEXT: abs v0.4h, v0.4h
349-
; CHECK-NEXT: abs v1.4h, v1.4h
350-
; CHECK-NEXT: mov v0.d[1], v1.d[0]
343+
; CHECK-NEXT: sshll v1.4s, v0.4h, #0
344+
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
345+
; CHECK-NEXT: abs v0.4s, v0.4s
346+
; CHECK-NEXT: abs v1.4s, v1.4s
347+
; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
351348
; CHECK-NEXT: ret
352349
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
353350
%sub = sub <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, %zextsrc1

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