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fixup! [AMDGPU] Ensure non-reserved CSR spilled regs are live-in
1 parent bb8aab7 commit 07bd851

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2 files changed

+17
-18
lines changed

2 files changed

+17
-18
lines changed

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -996,10 +996,10 @@ void SIFrameLowering::emitCSRSpillStores(
996996
}
997997
};
998998

999-
for (const auto &Reg : WWMScratchRegs) {
1000-
if (!MRI.isReserved(Reg.first)) {
1001-
MRI.addLiveIn(Reg.first);
1002-
MBB.addLiveIn(Reg.first);
999+
for (const auto &Reg : make_first_range(WWMScratchRegs)) {
1000+
if (!MRI.isReserved(Reg)) {
1001+
MRI.addLiveIn(Reg);
1002+
MBB.addLiveIn(Reg);
10031003
}
10041004
}
10051005
StoreWWMRegisters(WWMScratchRegs);

llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.ll

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -36,12 +36,12 @@ bb30: ; preds = %bb29
3636
br i1 %arg5, label %bb31, label %bb32
3737

3838
bb31: ; preds = %bb30
39-
store i1 false, ptr addrspace(5) null, align 2147483648
39+
store i1 false, ptr addrspace(5) %arg17, align 8
4040
br label %bb55
4141

4242
bb32: ; preds = %bb30
43-
store float %arg3, ptr addrspace(5) null, align 2147483648
44-
store float %arg7, ptr addrspace(5) %arg10, align 2147483648
43+
store float %arg3, ptr addrspace(5) %arg25, align 8
44+
store float %arg7, ptr addrspace(5) %arg10, align 8
4545
br i1 %arg2, label %bb34, label %bb33
4646

4747
bb33: ; preds = %bb32
@@ -52,11 +52,11 @@ bb34: ; preds = %bb33, %bb32
5252
br i1 %arg11, label %bb37, label %bb36
5353

5454
bb35: ; preds = %bb33
55-
store float 0.000000e+00, ptr addrspace(5) null, align 2147483648
55+
store float 0.000000e+00, ptr addrspace(5) %arg25, align 8
5656
ret i1 false
5757

5858
bb36: ; preds = %bb34
59-
store i32 1, ptr addrspace(5) null, align 2147483648
59+
store i32 1, ptr addrspace(5) %arg17, align 8
6060
br label %bb29
6161

6262
bb37: ; preds = %bb34
@@ -68,22 +68,22 @@ bb38: ; preds = %bb37
6868
br i1 %arg4, label %bb39, label %bb53
6969

7070
bb39: ; preds = %bb38
71-
store float %arg1, ptr addrspace(5) null, align 2147483648
71+
store float %arg1, ptr addrspace(5) %arg25, align 8
7272
%load40 = load float, ptr %arg15, align 8
7373
call void @llvm.memcpy.p5.p0.i64(ptr addrspace(5) %arg25, ptr %arg24, i64 12, i1 false)
7474
%load41 = load float, ptr %arg16, align 4
7575
call void @llvm.memcpy.p5.p0.i64(ptr addrspace(5) %arg17, ptr null, i64 36, i1 false)
7676
%load42 = load float, ptr %arg18, align 4
7777
%load43 = load float, ptr %arg19, align 4
78-
store float 0x7FF8000000000000, ptr addrspace(5) null, align 2147483648
78+
store float 0x7FF8000000000000, ptr addrspace(5) %arg25, align 8
7979
%load44 = load float, ptr %arg14, align 16
80-
store float %load44, ptr addrspace(5) null, align 2147483648
80+
store float %load44, ptr addrspace(5) %arg25, align 8
8181
%fcmp45 = fcmp ole float %arg9, 0.000000e+00
8282
br i1 %fcmp45, label %bb29, label %bb46
8383

8484
bb46: ; preds = %bb39
8585
%fsub = fsub float %arg8, %load40
86-
store float %fsub, ptr addrspace(5) null, align 2147483648
86+
store float %fsub, ptr addrspace(5) %arg25, align 8
8787
%fadd = fadd float %load42, %load43
8888
br i1 %arg, label %bb29, label %bb47
8989

@@ -96,12 +96,12 @@ bb48: ; preds = %bb47
9696
bb49: ; preds = %bb48
9797
store float 0.000000e+00, ptr %arg23, align 4
9898
store float 0.000000e+00, ptr %arg22, align 8
99-
store float %fadd, ptr addrspace(5) null, align 2147483648
99+
store float %fadd, ptr addrspace(5) %arg25, align 8
100100
%load50 = load float, ptr %arg20, align 4
101101
%fdiv = fdiv float %load41, %load50
102-
store float %fdiv, ptr addrspace(5) null, align 2147483648
102+
store float %fdiv, ptr addrspace(5) %arg25, align 8
103103
%load51 = load float, ptr %arg13, align 16
104-
store float %load51, ptr addrspace(5) null, align 2147483648
104+
store float %load51, ptr addrspace(5) %arg25, align 8
105105
store float 1.000000e+00, ptr %arg21, align 4
106106
br label %bb29
107107

@@ -115,11 +115,10 @@ bb54: ; preds = %bb37
115115
ret i1 true
116116

117117
bb55: ; preds = %bb31, %bb29
118-
%load56 = load i1, ptr addrspace(5) null, align 2147483648
118+
%load56 = load i1, ptr addrspace(5) null, align 8
119119
ret i1 %load56
120120
}
121121

122-
; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite)
123122
declare void @llvm.memcpy.p5.p0.i64(ptr addrspace(5) noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1
124123

125124
attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }

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