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AZero13AZero13
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[SelectionDAG] Move sign pattern check from AArch64 and ARM to general SelectionDAG (#151736)
This works on all cases much like the XOR case above it in SelectionDAG.
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4 files changed

+34
-44
lines changed

4 files changed

+34
-44
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29025,13 +29025,27 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
2902529025
((N1C->isAllOnes() && CC == ISD::SETGT) ||
2902629026
(N1C->isZero() && CC == ISD::SETLT)) &&
2902729027
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) {
29028-
SDValue ASR = DAG.getNode(
29029-
ISD::SRA, DL, CmpOpVT, N0,
29030-
DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT));
29031-
return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT),
29028+
SDValue ASHR =
29029+
DAG.getNode(ISD::SRA, DL, CmpOpVT, N0,
29030+
DAG.getShiftAmountConstant(
29031+
CmpOpVT.getScalarSizeInBits() - 1, CmpOpVT, DL));
29032+
return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASHR, DL, VT),
2903229033
DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT));
2903329034
}
2903429035

29036+
// Fold sign pattern select_cc setgt X, -1, 1, -1 -> or (ashr X, BW-1), 1
29037+
if (CC == ISD::SETGT && N1C && N2C && N3C && N1C->isAllOnes() &&
29038+
N2C->isOne() && N3C->isAllOnes() &&
29039+
!TLI.shouldAvoidTransformToShift(CmpOpVT,
29040+
CmpOpVT.getScalarSizeInBits() - 1)) {
29041+
SDValue ASHR =
29042+
DAG.getNode(ISD::SRA, DL, CmpOpVT, N0,
29043+
DAG.getShiftAmountConstant(
29044+
CmpOpVT.getScalarSizeInBits() - 1, CmpOpVT, DL));
29045+
return DAG.getNode(ISD::OR, DL, VT, DAG.getSExtOrTrunc(ASHR, DL, VT),
29046+
DAG.getConstant(1, DL, VT));
29047+
}
29048+
2903529049
if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG))
2903629050
return S;
2903729051
if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG))

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -11364,18 +11364,6 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
1136411364
ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1136511365
ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1136611366
ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
11367-
// Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
11368-
// into (OR (ASR lhs, N-1), 1), which requires less instructions for the
11369-
// supported types.
11370-
if (CC == ISD::SETGT && RHSC && RHSC->isAllOnes() && CTVal && CFVal &&
11371-
CTVal->isOne() && CFVal->isAllOnes() &&
11372-
LHS.getValueType() == TVal.getValueType()) {
11373-
EVT VT = LHS.getValueType();
11374-
SDValue Shift =
11375-
DAG.getNode(ISD::SRA, DL, VT, LHS,
11376-
DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
11377-
return DAG.getNode(ISD::OR, DL, VT, Shift, DAG.getConstant(1, DL, VT));
11378-
}
1137911367

1138011368
// Check for SMAX(lhs, 0) and SMIN(lhs, 0) patterns.
1138111369
// (SELECT_CC setgt, lhs, 0, lhs, 0) -> (BIC lhs, (SRA lhs, typesize-1))

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5521,18 +5521,6 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
55215521
ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
55225522
ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
55235523
if (Op.getValueType().isInteger()) {
5524-
// Check for sign pattern (SELECT_CC setgt, iN lhs, -1, 1, -1) and transform
5525-
// into (OR (ASR lhs, N-1), 1), which requires less instructions for the
5526-
// supported types.
5527-
if (CC == ISD::SETGT && RHSC && RHSC->isAllOnes() && CTVal && CFVal &&
5528-
CTVal->isOne() && CFVal->isAllOnes() &&
5529-
LHS.getValueType() == TrueVal.getValueType()) {
5530-
EVT VT = LHS.getValueType();
5531-
SDValue Shift =
5532-
DAG.getNode(ISD::SRA, dl, VT, LHS,
5533-
DAG.getConstant(VT.getSizeInBits() - 1, dl, VT));
5534-
return DAG.getNode(ISD::OR, dl, VT, Shift, DAG.getConstant(1, dl, VT));
5535-
}
55365524

55375525
// Check for SMAX(lhs, 0) and SMIN(lhs, 0) patterns.
55385526
// (SELECT_CC setgt, lhs, 0, lhs, 0) -> (BIC lhs, (SRA lhs, typesize-1))

‎llvm/test/CodeGen/ARM/cmp-select-sign.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -75,31 +75,31 @@ define i4 @sign_i4(i4 %a) {
7575
define i8 @sign_i8(i8 %a) {
7676
; ARM-LABEL: sign_i8:
7777
; ARM: @ %bb.0:
78-
; ARM-NEXT: lsl r0, r0, #24
78+
; ARM-NEXT: sxtb r0, r0
7979
; ARM-NEXT: mov r1, #1
80-
; ARM-NEXT: orr r0, r1, r0, asr #31
80+
; ARM-NEXT: orr r0, r1, r0, asr #7
8181
; ARM-NEXT: bx lr
8282
;
8383
; THUMB-LABEL: sign_i8:
8484
; THUMB: @ %bb.0:
85-
; THUMB-NEXT: lsls r0, r0, #24
86-
; THUMB-NEXT: asrs r1, r0, #31
85+
; THUMB-NEXT: sxtb r0, r0
86+
; THUMB-NEXT: asrs r1, r0, #7
8787
; THUMB-NEXT: movs r0, #1
8888
; THUMB-NEXT: orrs r0, r1
8989
; THUMB-NEXT: bx lr
9090
;
9191
; THUMB2-LABEL: sign_i8:
9292
; THUMB2: @ %bb.0:
93-
; THUMB2-NEXT: lsls r0, r0, #24
93+
; THUMB2-NEXT: sxtb r0, r0
9494
; THUMB2-NEXT: movs r1, #1
95-
; THUMB2-NEXT: orr.w r0, r1, r0, asr #31
95+
; THUMB2-NEXT: orr.w r0, r1, r0, asr #7
9696
; THUMB2-NEXT: bx lr
9797
;
9898
; THUMBV8-LABEL: sign_i8:
9999
; THUMBV8: @ %bb.0:
100-
; THUMBV8-NEXT: lsls r0, r0, #24
100+
; THUMBV8-NEXT: sxtb r0, r0
101101
; THUMBV8-NEXT: movs r1, #1
102-
; THUMBV8-NEXT: orr.w r0, r1, r0, asr #31
102+
; THUMBV8-NEXT: orr.w r0, r1, r0, asr #7
103103
; THUMBV8-NEXT: bx lr
104104
%c = icmp sgt i8 %a, -1
105105
%res = select i1 %c, i8 1, i8 -1
@@ -109,31 +109,31 @@ define i8 @sign_i8(i8 %a) {
109109
define i16 @sign_i16(i16 %a) {
110110
; ARM-LABEL: sign_i16:
111111
; ARM: @ %bb.0:
112-
; ARM-NEXT: lsl r0, r0, #16
112+
; ARM-NEXT: sxth r0, r0
113113
; ARM-NEXT: mov r1, #1
114-
; ARM-NEXT: orr r0, r1, r0, asr #31
114+
; ARM-NEXT: orr r0, r1, r0, asr #15
115115
; ARM-NEXT: bx lr
116116
;
117117
; THUMB-LABEL: sign_i16:
118118
; THUMB: @ %bb.0:
119-
; THUMB-NEXT: lsls r0, r0, #16
120-
; THUMB-NEXT: asrs r1, r0, #31
119+
; THUMB-NEXT: sxth r0, r0
120+
; THUMB-NEXT: asrs r1, r0, #15
121121
; THUMB-NEXT: movs r0, #1
122122
; THUMB-NEXT: orrs r0, r1
123123
; THUMB-NEXT: bx lr
124124
;
125125
; THUMB2-LABEL: sign_i16:
126126
; THUMB2: @ %bb.0:
127-
; THUMB2-NEXT: lsls r0, r0, #16
127+
; THUMB2-NEXT: sxth r0, r0
128128
; THUMB2-NEXT: movs r1, #1
129-
; THUMB2-NEXT: orr.w r0, r1, r0, asr #31
129+
; THUMB2-NEXT: orr.w r0, r1, r0, asr #15
130130
; THUMB2-NEXT: bx lr
131131
;
132132
; THUMBV8-LABEL: sign_i16:
133133
; THUMBV8: @ %bb.0:
134-
; THUMBV8-NEXT: lsls r0, r0, #16
134+
; THUMBV8-NEXT: sxth r0, r0
135135
; THUMBV8-NEXT: movs r1, #1
136-
; THUMBV8-NEXT: orr.w r0, r1, r0, asr #31
136+
; THUMBV8-NEXT: orr.w r0, r1, r0, asr #15
137137
; THUMBV8-NEXT: bx lr
138138
%c = icmp sgt i16 %a, -1
139139
%res = select i1 %c, i16 1, i16 -1

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