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davemgreendavemgreen
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[AArch64][GlobalISel] Add extra GISel test coverage. NFC
This is essentially from performAddSubCombine. addsub.ll has been cleaned up a little in the process.
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9 files changed

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‎llvm/test/CodeGen/AArch64/aarch64-isel-csinc-type.ll

Lines changed: 90 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-- -o - < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-- -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64-- -global-isel -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
; Verify that we can fold csneg/csel into csinc instruction.
56

@@ -8,12 +9,20 @@ target triple = "aarch64-unknown-linux-gnu"
89

910
; char csinc1 (char a, char b) { return !a ? b+1 : b+3; }
1011
define i8 @csinc1(i8 %a, i8 %b) local_unnamed_addr #0 {
11-
; CHECK-LABEL: csinc1:
12-
; CHECK: // %bb.0: // %entry
13-
; CHECK-NEXT: tst w0, #0xff
14-
; CHECK-NEXT: add w8, w1, #3
15-
; CHECK-NEXT: csinc w0, w8, w1, ne
16-
; CHECK-NEXT: ret
12+
; CHECK-SD-LABEL: csinc1:
13+
; CHECK-SD: // %bb.0: // %entry
14+
; CHECK-SD-NEXT: tst w0, #0xff
15+
; CHECK-SD-NEXT: add w8, w1, #3
16+
; CHECK-SD-NEXT: csinc w0, w8, w1, ne
17+
; CHECK-SD-NEXT: ret
18+
;
19+
; CHECK-GI-LABEL: csinc1:
20+
; CHECK-GI: // %bb.0: // %entry
21+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
22+
; CHECK-GI-NEXT: tst w0, #0xff
23+
; CHECK-GI-NEXT: csinc w8, w8, wzr, ne
24+
; CHECK-GI-NEXT: add w0, w8, w1
25+
; CHECK-GI-NEXT: ret
1726
entry:
1827
%tobool.not = icmp eq i8 %a, 0
1928
%cond.v = select i1 %tobool.not, i8 1, i8 3
@@ -23,12 +32,20 @@ entry:
2332

2433
; short csinc2 (short a, short b) { return !a ? b+1 : b+3; }
2534
define i16 @csinc2(i16 %a, i16 %b) local_unnamed_addr #0 {
26-
; CHECK-LABEL: csinc2:
27-
; CHECK: // %bb.0: // %entry
28-
; CHECK-NEXT: tst w0, #0xffff
29-
; CHECK-NEXT: add w8, w1, #3
30-
; CHECK-NEXT: csinc w0, w8, w1, ne
31-
; CHECK-NEXT: ret
35+
; CHECK-SD-LABEL: csinc2:
36+
; CHECK-SD: // %bb.0: // %entry
37+
; CHECK-SD-NEXT: tst w0, #0xffff
38+
; CHECK-SD-NEXT: add w8, w1, #3
39+
; CHECK-SD-NEXT: csinc w0, w8, w1, ne
40+
; CHECK-SD-NEXT: ret
41+
;
42+
; CHECK-GI-LABEL: csinc2:
43+
; CHECK-GI: // %bb.0: // %entry
44+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
45+
; CHECK-GI-NEXT: tst w0, #0xffff
46+
; CHECK-GI-NEXT: csinc w8, w8, wzr, ne
47+
; CHECK-GI-NEXT: add w0, w8, w1
48+
; CHECK-GI-NEXT: ret
3249
entry:
3350
%tobool.not = icmp eq i16 %a, 0
3451
%cond.v = select i1 %tobool.not, i16 1, i16 3
@@ -38,12 +55,20 @@ entry:
3855

3956
; int csinc3 (int a, int b) { return !a ? b+1 : b+3; }
4057
define i32 @csinc3(i32 %a, i32 %b) local_unnamed_addr #0 {
41-
; CHECK-LABEL: csinc3:
42-
; CHECK: // %bb.0: // %entry
43-
; CHECK-NEXT: cmp w0, #0
44-
; CHECK-NEXT: add w8, w1, #3
45-
; CHECK-NEXT: csinc w0, w8, w1, ne
46-
; CHECK-NEXT: ret
58+
; CHECK-SD-LABEL: csinc3:
59+
; CHECK-SD: // %bb.0: // %entry
60+
; CHECK-SD-NEXT: cmp w0, #0
61+
; CHECK-SD-NEXT: add w8, w1, #3
62+
; CHECK-SD-NEXT: csinc w0, w8, w1, ne
63+
; CHECK-SD-NEXT: ret
64+
;
65+
; CHECK-GI-LABEL: csinc3:
66+
; CHECK-GI: // %bb.0: // %entry
67+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
68+
; CHECK-GI-NEXT: cmp w0, #0
69+
; CHECK-GI-NEXT: csinc w8, w8, wzr, ne
70+
; CHECK-GI-NEXT: add w0, w8, w1
71+
; CHECK-GI-NEXT: ret
4772
entry:
4873
%tobool.not = icmp eq i32 %a, 0
4974
%cond.v = select i1 %tobool.not, i32 1, i32 3
@@ -53,12 +78,20 @@ entry:
5378

5479
; long long csinc4 (long long a, long long b) { return !a ? b+1 : b+3; }
5580
define i64 @csinc4(i64 %a, i64 %b) local_unnamed_addr #0 {
56-
; CHECK-LABEL: csinc4:
57-
; CHECK: // %bb.0: // %entry
58-
; CHECK-NEXT: cmp x0, #0
59-
; CHECK-NEXT: add x8, x1, #3
60-
; CHECK-NEXT: csinc x0, x8, x1, ne
61-
; CHECK-NEXT: ret
81+
; CHECK-SD-LABEL: csinc4:
82+
; CHECK-SD: // %bb.0: // %entry
83+
; CHECK-SD-NEXT: cmp x0, #0
84+
; CHECK-SD-NEXT: add x8, x1, #3
85+
; CHECK-SD-NEXT: csinc x0, x8, x1, ne
86+
; CHECK-SD-NEXT: ret
87+
;
88+
; CHECK-GI-LABEL: csinc4:
89+
; CHECK-GI: // %bb.0: // %entry
90+
; CHECK-GI-NEXT: mov w8, #3 // =0x3
91+
; CHECK-GI-NEXT: cmp x0, #0
92+
; CHECK-GI-NEXT: csinc x8, x8, xzr, ne
93+
; CHECK-GI-NEXT: add x0, x8, x1
94+
; CHECK-GI-NEXT: ret
6295
entry:
6396
%tobool.not = icmp eq i64 %a, 0
6497
%cond.v = select i1 %tobool.not, i64 1, i64 3
@@ -68,12 +101,21 @@ entry:
68101

69102
; long long csinc8 (long long a, long long b) { return a ? b-1 : b+1; }
70103
define i64 @csinc8(i64 %a, i64 %b) {
71-
; CHECK-LABEL: csinc8:
72-
; CHECK: // %bb.0: // %entry
73-
; CHECK-NEXT: sub x8, x1, #1
74-
; CHECK-NEXT: cmp x0, #0
75-
; CHECK-NEXT: csinc x0, x8, x1, ne
76-
; CHECK-NEXT: ret
104+
; CHECK-SD-LABEL: csinc8:
105+
; CHECK-SD: // %bb.0: // %entry
106+
; CHECK-SD-NEXT: sub x8, x1, #1
107+
; CHECK-SD-NEXT: cmp x0, #0
108+
; CHECK-SD-NEXT: csinc x0, x8, x1, ne
109+
; CHECK-SD-NEXT: ret
110+
;
111+
; CHECK-GI-LABEL: csinc8:
112+
; CHECK-GI: // %bb.0: // %entry
113+
; CHECK-GI-NEXT: cmp x0, #0
114+
; CHECK-GI-NEXT: cset w8, ne
115+
; CHECK-GI-NEXT: sbfx x8, x8, #0, #1
116+
; CHECK-GI-NEXT: orr x8, x8, #0x1
117+
; CHECK-GI-NEXT: add x0, x8, x1
118+
; CHECK-GI-NEXT: ret
77119
entry:
78120
%tobool.not = icmp eq i64 %a, 0
79121
%cond.v = select i1 %tobool.not, i64 1, i64 -1
@@ -83,15 +125,26 @@ entry:
83125

84126
; long long csinc9 (long long a, long long b) { return a ? b+1 : b-1; }
85127
define i64 @csinc9(i64 %a, i64 %b) {
86-
; CHECK-LABEL: csinc9:
87-
; CHECK: // %bb.0: // %entry
88-
; CHECK-NEXT: sub x8, x1, #1
89-
; CHECK-NEXT: cmp x0, #0
90-
; CHECK-NEXT: csinc x0, x8, x1, eq
91-
; CHECK-NEXT: ret
128+
; CHECK-SD-LABEL: csinc9:
129+
; CHECK-SD: // %bb.0: // %entry
130+
; CHECK-SD-NEXT: sub x8, x1, #1
131+
; CHECK-SD-NEXT: cmp x0, #0
132+
; CHECK-SD-NEXT: csinc x0, x8, x1, eq
133+
; CHECK-SD-NEXT: ret
134+
;
135+
; CHECK-GI-LABEL: csinc9:
136+
; CHECK-GI: // %bb.0: // %entry
137+
; CHECK-GI-NEXT: cmp x0, #0
138+
; CHECK-GI-NEXT: cset w8, eq
139+
; CHECK-GI-NEXT: sbfx x8, x8, #0, #1
140+
; CHECK-GI-NEXT: orr x8, x8, #0x1
141+
; CHECK-GI-NEXT: add x0, x8, x1
142+
; CHECK-GI-NEXT: ret
92143
entry:
93144
%tobool.not = icmp eq i64 %a, 0
94145
%cond.v = select i1 %tobool.not, i64 -1, i64 1
95146
%cond = add nsw i64 %cond.v, %b
96147
ret i64 %cond
97148
}
149+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
150+
; CHECK: {{.*}}

‎llvm/test/CodeGen/AArch64/add-extract.ll

Lines changed: 100 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,62 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
5-
; CHECK-LABEL: add_i64_ext_load:
6-
; CHECK: // %bb.0:
7-
; CHECK-NEXT: ldr d1, [x0]
8-
; CHECK-NEXT: add d0, d0, d1
9-
; CHECK-NEXT: fmov x0, d0
10-
; CHECK-NEXT: ret
6+
; CHECK-SD-LABEL: add_i64_ext_load:
7+
; CHECK-SD: // %bb.0:
8+
; CHECK-SD-NEXT: ldr d1, [x0]
9+
; CHECK-SD-NEXT: add d0, d0, d1
10+
; CHECK-SD-NEXT: fmov x0, d0
11+
; CHECK-SD-NEXT: ret
12+
;
13+
; CHECK-GI-LABEL: add_i64_ext_load:
14+
; CHECK-GI: // %bb.0:
15+
; CHECK-GI-NEXT: fmov x9, d0
16+
; CHECK-GI-NEXT: ldr x8, [x0]
17+
; CHECK-GI-NEXT: add x0, x9, x8
18+
; CHECK-GI-NEXT: ret
1119
%a = extractelement <1 x i64> %A, i32 0
1220
%b = load i64, ptr %B
1321
%c = add i64 %a, %b
1422
ret i64 %c
1523
}
1624

1725
define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
18-
; CHECK-LABEL: sub_i64_ext_load:
19-
; CHECK: // %bb.0:
20-
; CHECK-NEXT: ldr d1, [x0]
21-
; CHECK-NEXT: sub d0, d0, d1
22-
; CHECK-NEXT: fmov x0, d0
23-
; CHECK-NEXT: ret
26+
; CHECK-SD-LABEL: sub_i64_ext_load:
27+
; CHECK-SD: // %bb.0:
28+
; CHECK-SD-NEXT: ldr d1, [x0]
29+
; CHECK-SD-NEXT: sub d0, d0, d1
30+
; CHECK-SD-NEXT: fmov x0, d0
31+
; CHECK-SD-NEXT: ret
32+
;
33+
; CHECK-GI-LABEL: sub_i64_ext_load:
34+
; CHECK-GI: // %bb.0:
35+
; CHECK-GI-NEXT: fmov x9, d0
36+
; CHECK-GI-NEXT: ldr x8, [x0]
37+
; CHECK-GI-NEXT: sub x0, x9, x8
38+
; CHECK-GI-NEXT: ret
2439
%a = extractelement <1 x i64> %A, i32 0
2540
%b = load i64, ptr %B
2641
%c = sub i64 %a, %b
2742
ret i64 %c
2843
}
2944

3045
define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {
31-
; CHECK-LABEL: add_i64_ext_load_store:
32-
; CHECK: // %bb.0:
33-
; CHECK-NEXT: ldr d1, [x0]
34-
; CHECK-NEXT: add d0, d0, d1
35-
; CHECK-NEXT: str d0, [x0]
36-
; CHECK-NEXT: ret
46+
; CHECK-SD-LABEL: add_i64_ext_load_store:
47+
; CHECK-SD: // %bb.0:
48+
; CHECK-SD-NEXT: ldr d1, [x0]
49+
; CHECK-SD-NEXT: add d0, d0, d1
50+
; CHECK-SD-NEXT: str d0, [x0]
51+
; CHECK-SD-NEXT: ret
52+
;
53+
; CHECK-GI-LABEL: add_i64_ext_load_store:
54+
; CHECK-GI: // %bb.0:
55+
; CHECK-GI-NEXT: fmov x9, d0
56+
; CHECK-GI-NEXT: ldr x8, [x0]
57+
; CHECK-GI-NEXT: add x8, x9, x8
58+
; CHECK-GI-NEXT: str x8, [x0]
59+
; CHECK-GI-NEXT: ret
3760
%a = extractelement <1 x i64> %A, i32 0
3861
%b = load i64, ptr %B
3962
%c = add i64 %a, %b
@@ -55,39 +78,62 @@ define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {
5578
}
5679

5780
define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {
58-
; CHECK-LABEL: add_i64_ext_ext:
59-
; CHECK: // %bb.0:
60-
; CHECK-NEXT: add d0, d0, d1
61-
; CHECK-NEXT: fmov x0, d0
62-
; CHECK-NEXT: ret
81+
; CHECK-SD-LABEL: add_i64_ext_ext:
82+
; CHECK-SD: // %bb.0:
83+
; CHECK-SD-NEXT: add d0, d0, d1
84+
; CHECK-SD-NEXT: fmov x0, d0
85+
; CHECK-SD-NEXT: ret
86+
;
87+
; CHECK-GI-LABEL: add_i64_ext_ext:
88+
; CHECK-GI: // %bb.0:
89+
; CHECK-GI-NEXT: fmov x8, d0
90+
; CHECK-GI-NEXT: fmov x9, d1
91+
; CHECK-GI-NEXT: add x0, x8, x9
92+
; CHECK-GI-NEXT: ret
6393
%a = extractelement <1 x i64> %A, i32 0
6494
%b = extractelement <1 x i64> %B, i32 0
6595
%c = add i64 %a, %b
6696
ret i64 %c
6797
}
6898

6999
define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
70-
; CHECK-LABEL: add_i32_ext_load:
71-
; CHECK: // %bb.0:
72-
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
73-
; CHECK-NEXT: fmov w9, s0
74-
; CHECK-NEXT: ldr w8, [x0]
75-
; CHECK-NEXT: add w0, w9, w8
76-
; CHECK-NEXT: ret
100+
; CHECK-SD-LABEL: add_i32_ext_load:
101+
; CHECK-SD: // %bb.0:
102+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
103+
; CHECK-SD-NEXT: fmov w9, s0
104+
; CHECK-SD-NEXT: ldr w8, [x0]
105+
; CHECK-SD-NEXT: add w0, w9, w8
106+
; CHECK-SD-NEXT: ret
107+
;
108+
; CHECK-GI-LABEL: add_i32_ext_load:
109+
; CHECK-GI: // %bb.0:
110+
; CHECK-GI-NEXT: fmov w9, s0
111+
; CHECK-GI-NEXT: ldr w8, [x0]
112+
; CHECK-GI-NEXT: add w0, w9, w8
113+
; CHECK-GI-NEXT: ret
77114
%a = extractelement <1 x i32> %A, i32 0
78115
%b = load i32, ptr %B
79116
%c = add i32 %a, %b
80117
ret i32 %c
81118
}
82119

83120
define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
84-
; CHECK-LABEL: add_i64_ext_ext_test1:
85-
; CHECK: // %bb.0:
86-
; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
87-
; CHECK-NEXT: add d0, d0, d1
88-
; CHECK-NEXT: add d0, d0, d2
89-
; CHECK-NEXT: fmov x0, d0
90-
; CHECK-NEXT: ret
121+
; CHECK-SD-LABEL: add_i64_ext_ext_test1:
122+
; CHECK-SD: // %bb.0:
123+
; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
124+
; CHECK-SD-NEXT: add d0, d0, d1
125+
; CHECK-SD-NEXT: add d0, d0, d2
126+
; CHECK-SD-NEXT: fmov x0, d0
127+
; CHECK-SD-NEXT: ret
128+
;
129+
; CHECK-GI-LABEL: add_i64_ext_ext_test1:
130+
; CHECK-GI: // %bb.0:
131+
; CHECK-GI-NEXT: mov x8, v1.d[1]
132+
; CHECK-GI-NEXT: fmov x9, d0
133+
; CHECK-GI-NEXT: fmov x10, d1
134+
; CHECK-GI-NEXT: add x9, x9, x10
135+
; CHECK-GI-NEXT: add x0, x9, x8
136+
; CHECK-GI-NEXT: ret
91137
%a = extractelement <1 x i64> %A, i32 0
92138
%b = extractelement <2 x i64> %B, i32 0
93139
%c = extractelement <2 x i64> %B, i32 1
@@ -97,13 +143,22 @@ define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
97143
}
98144

99145
define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
100-
; CHECK-LABEL: sub_i64_ext_ext_test1:
101-
; CHECK: // %bb.0:
102-
; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
103-
; CHECK-NEXT: sub d0, d0, d1
104-
; CHECK-NEXT: sub d0, d0, d2
105-
; CHECK-NEXT: fmov x0, d0
106-
; CHECK-NEXT: ret
146+
; CHECK-SD-LABEL: sub_i64_ext_ext_test1:
147+
; CHECK-SD: // %bb.0:
148+
; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
149+
; CHECK-SD-NEXT: sub d0, d0, d1
150+
; CHECK-SD-NEXT: sub d0, d0, d2
151+
; CHECK-SD-NEXT: fmov x0, d0
152+
; CHECK-SD-NEXT: ret
153+
;
154+
; CHECK-GI-LABEL: sub_i64_ext_ext_test1:
155+
; CHECK-GI: // %bb.0:
156+
; CHECK-GI-NEXT: mov x8, v1.d[1]
157+
; CHECK-GI-NEXT: fmov x9, d0
158+
; CHECK-GI-NEXT: fmov x10, d1
159+
; CHECK-GI-NEXT: sub x9, x9, x10
160+
; CHECK-GI-NEXT: sub x0, x9, x8
161+
; CHECK-GI-NEXT: ret
107162
%a = extractelement <1 x i64> %A, i32 0
108163
%b = extractelement <2 x i64> %B, i32 0
109164
%c = extractelement <2 x i64> %B, i32 1

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