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1 parent 486ff10 commit 428d03aCopy full SHA for 428d03a
llvm/test/Transforms/LoopVectorize/RISCV/interleaved-store-with-gap.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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-; RUN: opt -mtriple=riscv64 -mattr=+v -passes=loop-vectorize -mattr=+v \
+; RUN: opt -mtriple=riscv64 -mattr=+v -passes=loop-vectorize \
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; RUN: -scalable-vectorization=off -enable-masked-interleaved-mem-accesses \
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; RUN: -force-vector-interleave=1 -riscv-v-vector-bits-min=1024 -S < %s | FileCheck %s
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