Revert "[RISCV][TTI] Enable masked interleave access for scalable vector (#149981)"

This reverts commit ee3a771.

Causes an assertion for the zvl1024b RISC-V build configuration. See
comment with reproducer at
<#149981 (comment)>

Author: asb

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -979,12 +979,10 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost(
     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
     bool UseMaskForCond, bool UseMaskForGaps) const {
 
-  // The interleaved memory access pass will lower (de)interleave ops combined
-  // with an adjacent appropriate memory to vlseg/vsseg intrinsics. vlseg/vsseg
-  // only support masking per-iteration (i.e. condition), not per-segment (i.e.
-  // gap).
-  // TODO: Support masked interleaved access for fixed length vector.
-  if ((isa<ScalableVectorType>(VecTy) || !UseMaskForCond) && !UseMaskForGaps &&
+  // The interleaved memory access pass will lower interleaved memory ops (i.e
+  // a load and store followed by a specific shuffle) to vlseg/vsseg
+  // intrinsics.
+  if (!UseMaskForCond && !UseMaskForGaps &&
       Factor <= TLI->getMaxSupportedInterleaveFactor()) {
     auto *VTy = cast<VectorType>(VecTy);
     std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(VTy);

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -398,10 +398,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
 
   bool enableInterleavedAccessVectorization() const override { return true; }
 
-  bool enableMaskedInterleavedAccessVectorization() const override {
-    return ST->hasVInstructions();
-  }
-
   unsigned getMinTripCountTailFoldingThreshold() const override;
 
   enum RISCVRegisterClass { GPRRC, FPRRC, VRRC };

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

@@ -1359,9 +1359,7 @@ class LoopVectorizationCostModel {
       return;
     // Override EVL styles if needed.
     // FIXME: Investigate opportunity for fixed vector factor.
-    // FIXME: Support interleave accesses.
     bool EVLIsLegal = UserIC <= 1 && IsScalableVF &&
-                      !InterleaveInfo.hasGroups() &&
                       TTI.hasActiveVectorLength() && !EnableVPlanNativePath;
     if (EVLIsLegal)
       return;