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[lld][LoongArch] GOT indirection to PC relative optimization.
In LoongArch, this optimization is only supported when relaxation is enabled. From: * pcalau12i $a0, %got_pc_hi20(sym_got) * ld.w/d $a0, $a0, %got_pc_lo12(sym_got) To: * pcalau12i $a0, %pc_hi20(sym) * addi.w/d $a0, $a0, %pc_lo12(sym) If the original code sequence can be relaxed into a single instruction `pcaddi`, this patch will not be taken (see https://). The implementation related to `got` is split into two locations because the `relax()` function is part of an iteration fixed-point algorithm. We should minimize it to achieve better linker performance. FIXME: Althouth the optimization has been performed, the GOT entries still exists, similarly to AArch64. Eliminating the entries may be require additional marking in the common code.
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lld/ELF/Arch/LoongArch.cpp

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ class LoongArch final : public TargetInfo {
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private:
4747
void tlsdescToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
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void tlsdescToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
49+
bool tryGotToPCRel(uint8_t *loc, const Relocation &rHi20,
50+
const Relocation &rLo12, uint64_t secAddr) const;
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};
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} // end anonymous namespace
5153

@@ -1151,6 +1153,54 @@ void LoongArch::tlsdescToLe(uint8_t *loc, const Relocation &rel,
11511153
}
11521154
}
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// Try GOT indirection to PC relative optimization when relaxation is enabled.
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// From:
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// * pcalau12i $a0, %got_pc_hi20(sym_got)
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// * ld.w/d $a0, $a0, %got_pc_lo12(sym_got)
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// To:
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// * pcalau12i $a0, %pc_hi20(sym)
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// * addi.w/d $a0, $a0, %pc_lo12(sym)
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//
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// FIXME: Althouth the optimization has been performed, the GOT entries still
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// exists, similarly to AArch64. Eliminating the entries may be require
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// additional marking in the common code.
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bool LoongArch::tryGotToPCRel(uint8_t *loc, const Relocation &rHi20,
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const Relocation &rLo12, uint64_t secAddr) const {
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if (!rHi20.sym->isDefined() || rHi20.sym->isPreemptible ||
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rHi20.sym->isGnuIFunc() ||
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(ctx.arg.isPic && !cast<Defined>(*rHi20.sym).section))
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return false;
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Symbol &sym = *rHi20.sym;
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uint64_t symLocal = sym.getVA(ctx) + rHi20.addend;
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// Check if the address difference is within +/-2GB range.
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// For simplicity, the range mentioned here is an approximate estimate and is
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// not fully equivalent to the entire region that PC-relative addressing can
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// cover.
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int64_t pageOffset =
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getLoongArchPage(symLocal) - getLoongArchPage(secAddr + rHi20.offset);
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if (!isInt<20>(pageOffset >> 12))
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return false;
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Relocation newRHi20 = {RE_LOONGARCH_PAGE_PC, R_LARCH_PCALA_HI20, rHi20.offset,
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rHi20.addend, &sym};
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Relocation newRLo12 = {R_ABS, R_LARCH_PCALA_LO12, rLo12.offset, rLo12.addend,
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&sym};
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const uint32_t currInsn = read32le(loc);
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const uint32_t nextInsn = read32le(loc + 4);
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uint64_t pageDelta =
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getLoongArchPageDelta(symLocal, secAddr + rHi20.offset, rHi20.type);
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// pcalau12i $a0, %pc_hi20
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write32le(loc, insn(PCALAU12I, getD5(currInsn), 0, 0));
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relocate(loc, newRHi20, pageDelta);
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// addi.w/d $a0, $a0, %pc_lo12
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write32le(loc + 4, insn(ctx.arg.is64 ? ADDI_D : ADDI_W, getD5(nextInsn),
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getJ5(nextInsn), 0));
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relocate(loc + 4, newRLo12, SignExtend64(symLocal, 64));
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return true;
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}
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// During TLSDESC GD_TO_IE, the converted code sequence always includes an
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// instruction related to the Lo12 relocation (ld.[wd]). To obtain correct val
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// in `getRelocTargetVA`, expr of this instruction should be adjusted to
@@ -1260,6 +1310,22 @@ void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
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tlsdescToLe(loc, rel, val);
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}
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continue;
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case RE_LOONGARCH_GOT_PAGE_PC:
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// In LoongArch, we try GOT indirection to PC relative optimization only
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// when relaxation is enabled. This approach avoids determining whether
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// relocation types are paired and whether the destination register of
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// pcalau12i is only used by the immediately following instruction.
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// Moreover, if the original code sequence can be relaxed to a single
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// instruction `pcaddi`, the first instruction will be removed and it will
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// not reach here.
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if (isPairRelaxable(relocs, i) && rel.type == R_LARCH_GOT_PC_HI20 &&
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relocs[i + 2].type == R_LARCH_GOT_PC_LO12 &&
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tryGotToPCRel(loc, rel, relocs[i + 2], secAddr)) {
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i = i + 3; // skip relocations R_LARCH_RELAX, R_LARCH_GOT_PC_LO12,
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// R_LARCH_RELAX
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continue;
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}
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break;
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default:
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break;
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}

lld/test/ELF/loongarch-relax-pc-hi20-lo12.s

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,24 +30,26 @@
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## offset = 0x410000 - 0x10000: 0x400 pages, page offset 0
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# NORELAX32-NEXT: 10000: pcalau12i $a0, 1024
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# NORELAX32-NEXT: addi.w $a0, $a0, 0
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## Not relaxation, convertion to PCRel.
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# NORELAX32-NEXT: pcalau12i $a0, 1024
34-
# NORELAX32-NEXT: ld.w $a0, $a0, 4
35+
# NORELAX32-NEXT: addi.w $a0, $a0, 0
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# NORELAX32-NEXT: pcalau12i $a0, 1024
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# NORELAX32-NEXT: addi.w $a0, $a0, 0
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# NORELAX32-NEXT: pcalau12i $a0, 1024
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# NORELAX32-NEXT: ld.w $a0, $a0, 4
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# NORELAX32-NEXT: addi.w $a0, $a0, 0
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4041
# NORELAX64-LABEL: <_start>:
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## offset exceed range of pcaddi
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## offset = 0x410000 - 0x10000: 0x400 pages, page offset 0
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# NORELAX64-NEXT: 10000: pcalau12i $a0, 1024
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# NORELAX64-NEXT: addi.d $a0, $a0, 0
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## Not relaxation, convertion to PCRel.
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# NORELAX64-NEXT: pcalau12i $a0, 1024
46-
# NORELAX64-NEXT: ld.d $a0, $a0, 8
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# NORELAX64-NEXT: addi.d $a0, $a0, 0
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# NORELAX64-NEXT: pcalau12i $a0, 1024
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# NORELAX64-NEXT: addi.d $a0, $a0, 0
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# NORELAX64-NEXT: pcalau12i $a0, 1024
50-
# NORELAX64-NEXT: ld.d $a0, $a0, 8
52+
# NORELAX64-NEXT: addi.d $a0, $a0, 0
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.section .text
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.global _start

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