Address review comments

david-arm · david-arm · commit d34df2606696 · 2025-07-30T09:51:24.000Z
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -25185,24 +25185,23 @@ static SDValue combineConcatVectorInterleave(SDNode *N, SelectionDAG &DAG) {
       return SDValue();
   }
 
-  SDValue InOp0 = FirstOp.getOperand(0);
-  if (!llvm::all_of(FirstOp->ops(),
-                    [&InOp0](SDValue Op) { return Op == InOp0; }))
+  if (!llvm::all_equal(FirstOp->op_values()))
     return SDValue();
 
   // We're concatenating all the sequential results of the same vector
   // interleave node. Now check if all inputs to the interleave are splats.
-  if (SDValue Splat = DAG.getSplatValue(InOp0)) {
-    SDLoc DL(N);
-    EVT SubVecTy = InOp0.getValueType();
-    // Create the wider type required.
-    EVT WideVecTy = EVT::getVectorVT(
-        *DAG.getContext(), SubVecTy.getScalarType(),
-        SubVecTy.getVectorElementCount() * N->getNumOperands());
-    return DAG.getSplat(WideVecTy, DL, Splat);
-  }
+  SDValue InOp0 = FirstOp.getOperand(0);
+  SDValue Splat = DAG.getSplatValue(InOp0);
+  if (!Splat)
+    return SDValue();
 
-  return SDValue();
+  SDLoc DL(N);
+  EVT SubVecTy = InOp0.getValueType();
+  // Create the wider type required.
+  EVT WideVecTy =
+      EVT::getVectorVT(*DAG.getContext(), SubVecTy.getScalarType(),
+                       SubVecTy.getVectorElementCount() * N->getNumOperands());
+  return DAG.getSplat(WideVecTy, DL, Splat);
 }
 
 // See if this is a simple CONCAT_VECTORS with no UNDEF operands, and if one of
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
@@ -216,20 +216,3 @@ define <4 x i16> @interleave2_diff_nonconst_splat_v4i16(i16 %a, i16 %b) {
 ;  %retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3))
 ;  ret <8 x i16> %retval
 ;}
-
-
-; Float declarations
-declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>)
-declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>)
-declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>)
-declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>)
-declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>)
-declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>)
-
-; Integer declarations
-declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>)
-declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
-declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
-declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
-declare <4 x i16> @llvm.vector.interleave2.v4i16(<2 x i16>, <2 x i16>)
-declare <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>)
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
@@ -618,33 +618,3 @@ define <vscale x 8 x i16> @interleave4_same_const_splat_nxv8i16() {
   %retval = call <vscale x 8 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3))
   ret <vscale x 8 x i16> %retval
 }
-
-; Float declarations
-declare <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half>, <vscale x 2 x half>)
-declare <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half>, <vscale x 4 x half>)
-declare <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half>, <vscale x 8 x half>)
-declare <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float>, <vscale x 2 x float>)
-declare <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)
-declare <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double>, <vscale x 2 x double>)
-
-; Integer declarations
-declare <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
-declare <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
-declare <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
-declare <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
-
-; Predicated
-declare <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
-declare <vscale x 16 x i1> @llvm.vector.interleave2.nxv16i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
-declare <vscale x 8 x i1> @llvm.vector.interleave2.nxv8i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
-declare <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
-
-; Illegal type size
-declare <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
-declare <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
-
-declare <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
-declare <vscale x 8 x i16> @llvm.vector.interleave2.nxv8i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
-declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
-declare <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
-declare <vscale x 8 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -14965,22 +14965,6 @@ define <vscale x 4 x i16> @interleave2_same_const_splat_nxv4i16() {
 }
 
 define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
-; SVE-LABEL: interleave2_diff_const_splat_nxv4i16:
-; SVE:       // %bb.0:
-; SVE-NEXT:    mov z0.d, #4 // =0x4
-; SVE-NEXT:    mov z1.d, #3 // =0x3
-; SVE-NEXT:    zip2 z2.d, z1.d, z0.d
-; SVE-NEXT:    zip1 z0.d, z1.d, z0.d
-; SVE-NEXT:    uzp1 z0.s, z0.s, z2.s
-; SVE-NEXT:    ret
-;
-; SME2-LABEL: interleave2_diff_const_splat_nxv4i16:
-; SME2:       // %bb.0:
-; SME2-NEXT:    mov z0.d, #4 // =0x4
-; SME2-NEXT:    mov z1.d, #3 // =0x3
-; SME2-NEXT:    zip { z0.d, z1.d }, z1.d, z0.d
-; SME2-NEXT:    uzp1 z0.s, z0.s, z1.s
-; SME2-NEXT:    ret
 ; V-LABEL: interleave2_diff_const_splat_nxv4i16:
 ; V:       # %bb.0:
 ; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
@@ -15045,26 +15029,6 @@ define <vscale x 4 x i16> @interleave2_same_nonconst_splat_nxv4i16(i16 %a) {
 }
 
 define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %b) {
-; SVE-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
-; SVE:       // %bb.0:
-; SVE-NEXT:    // kill: def $w1 killed $w1 def $x1
-; SVE-NEXT:    // kill: def $w0 killed $w0 def $x0
-; SVE-NEXT:    mov z0.d, x0
-; SVE-NEXT:    mov z1.d, x1
-; SVE-NEXT:    zip2 z2.d, z0.d, z1.d
-; SVE-NEXT:    zip1 z0.d, z0.d, z1.d
-; SVE-NEXT:    uzp1 z0.s, z0.s, z2.s
-; SVE-NEXT:    ret
-;
-; SME2-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
-; SME2:       // %bb.0:
-; SME2-NEXT:    // kill: def $w1 killed $w1 def $x1
-; SME2-NEXT:    // kill: def $w0 killed $w0 def $x0
-; SME2-NEXT:    mov z0.d, x0
-; SME2-NEXT:    mov z1.d, x1
-; SME2-NEXT:    zip { z0.d, z1.d }, z0.d, z1.d
-; SME2-NEXT:    uzp1 z0.s, z0.s, z1.s
-; SME2-NEXT:    ret
 ; V-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
 ; V:       # %bb.0:
 ; V-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma
