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AlexMacleanAlexMaclean
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[NVPTX] Cleanup various vestigial elements and fold together more table-gen (NFC) (#151447)
1 parent 507b879 commit d7f77b2

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9 files changed

+499
-758
lines changed

9 files changed

+499
-758
lines changed

‎llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -391,16 +391,6 @@ void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
391391
}
392392
}
393393

394-
void NVPTXInstPrinter::printOffseti32imm(const MCInst *MI, int OpNum,
395-
raw_ostream &O) {
396-
auto &Op = MI->getOperand(OpNum);
397-
assert(Op.isImm() && "Invalid operand");
398-
if (Op.getImm() != 0) {
399-
O << "+";
400-
printOperand(MI, OpNum, O);
401-
}
402-
}
403-
404394
void NVPTXInstPrinter::printHexu32imm(const MCInst *MI, int OpNum,
405395
raw_ostream &O) {
406396
int64_t Imm = MI->getOperand(OpNum).getImm();

‎llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@ class NVPTXInstPrinter : public MCInstPrinter {
4646
StringRef Modifier = {});
4747
void printMemOperand(const MCInst *MI, int OpNum, raw_ostream &O,
4848
StringRef Modifier = {});
49-
void printOffseti32imm(const MCInst *MI, int OpNum, raw_ostream &O);
5049
void printHexu32imm(const MCInst *MI, int OpNum, raw_ostream &O);
5150
void printProtoIdent(const MCInst *MI, int OpNum, raw_ostream &O);
5251
void printPrmtMode(const MCInst *MI, int OpNum, raw_ostream &O);

‎llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,15 +56,12 @@ static bool traverseMoveUse(MachineInstr &U, const MachineRegisterInfo &MRI,
5656
case NVPTX::LD_i16:
5757
case NVPTX::LD_i32:
5858
case NVPTX::LD_i64:
59-
case NVPTX::LD_i8:
6059
case NVPTX::LDV_i16_v2:
6160
case NVPTX::LDV_i16_v4:
6261
case NVPTX::LDV_i32_v2:
6362
case NVPTX::LDV_i32_v4:
6463
case NVPTX::LDV_i64_v2:
65-
case NVPTX::LDV_i64_v4:
66-
case NVPTX::LDV_i8_v2:
67-
case NVPTX::LDV_i8_v4: {
64+
case NVPTX::LDV_i64_v4: {
6865
LoadInsts.push_back(&U);
6966
return true;
7067
}

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

Lines changed: 38 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1003,14 +1003,10 @@ void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
10031003
// Helper function template to reduce amount of boilerplate code for
10041004
// opcode selection.
10051005
static std::optional<unsigned>
1006-
pickOpcodeForVT(MVT::SimpleValueType VT, std::optional<unsigned> Opcode_i8,
1007-
std::optional<unsigned> Opcode_i16,
1006+
pickOpcodeForVT(MVT::SimpleValueType VT, std::optional<unsigned> Opcode_i16,
10081007
std::optional<unsigned> Opcode_i32,
10091008
std::optional<unsigned> Opcode_i64) {
10101009
switch (VT) {
1011-
case MVT::i1:
1012-
case MVT::i8:
1013-
return Opcode_i8;
10141010
case MVT::f16:
10151011
case MVT::i16:
10161012
case MVT::bf16:
@@ -1078,8 +1074,8 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
10781074
Chain};
10791075

10801076
const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
1081-
const std::optional<unsigned> Opcode = pickOpcodeForVT(
1082-
TargetVT, NVPTX::LD_i8, NVPTX::LD_i16, NVPTX::LD_i32, NVPTX::LD_i64);
1077+
const std::optional<unsigned> Opcode =
1078+
pickOpcodeForVT(TargetVT, NVPTX::LD_i16, NVPTX::LD_i32, NVPTX::LD_i64);
10831079
if (!Opcode)
10841080
return false;
10851081

@@ -1164,17 +1160,15 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
11641160
default:
11651161
llvm_unreachable("Unexpected opcode");
11661162
case NVPTXISD::LoadV2:
1167-
Opcode =
1168-
pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v2, NVPTX::LDV_i16_v2,
1169-
NVPTX::LDV_i32_v2, NVPTX::LDV_i64_v2);
1163+
Opcode = pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i16_v2,
1164+
NVPTX::LDV_i32_v2, NVPTX::LDV_i64_v2);
11701165
break;
11711166
case NVPTXISD::LoadV4:
1172-
Opcode =
1173-
pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v4, NVPTX::LDV_i16_v4,
1174-
NVPTX::LDV_i32_v4, NVPTX::LDV_i64_v4);
1167+
Opcode = pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i16_v4,
1168+
NVPTX::LDV_i32_v4, NVPTX::LDV_i64_v4);
11751169
break;
11761170
case NVPTXISD::LoadV8:
1177-
Opcode = pickOpcodeForVT(EltVT.SimpleTy, {/* no v8i8 */}, {/* no v8i16 */},
1171+
Opcode = pickOpcodeForVT(EltVT.SimpleTy, {/* no v8i16 */},
11781172
NVPTX::LDV_i32_v8, {/* no v8i64 */});
11791173
break;
11801174
}
@@ -1230,22 +1224,21 @@ bool NVPTXDAGToDAGISel::tryLDG(MemSDNode *LD) {
12301224
default:
12311225
llvm_unreachable("Unexpected opcode");
12321226
case ISD::LOAD:
1233-
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_i8,
1234-
NVPTX::LD_GLOBAL_NC_i16, NVPTX::LD_GLOBAL_NC_i32,
1235-
NVPTX::LD_GLOBAL_NC_i64);
1227+
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_i16,
1228+
NVPTX::LD_GLOBAL_NC_i32, NVPTX::LD_GLOBAL_NC_i64);
12361229
break;
12371230
case NVPTXISD::LoadV2:
1238-
Opcode = pickOpcodeForVT(
1239-
TargetVT, NVPTX::LD_GLOBAL_NC_v2i8, NVPTX::LD_GLOBAL_NC_v2i16,
1240-
NVPTX::LD_GLOBAL_NC_v2i32, NVPTX::LD_GLOBAL_NC_v2i64);
1231+
Opcode =
1232+
pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_v2i16,
1233+
NVPTX::LD_GLOBAL_NC_v2i32, NVPTX::LD_GLOBAL_NC_v2i64);
12411234
break;
12421235
case NVPTXISD::LoadV4:
1243-
Opcode = pickOpcodeForVT(
1244-
TargetVT, NVPTX::LD_GLOBAL_NC_v4i8, NVPTX::LD_GLOBAL_NC_v4i16,
1245-
NVPTX::LD_GLOBAL_NC_v4i32, NVPTX::LD_GLOBAL_NC_v4i64);
1236+
Opcode =
1237+
pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_v4i16,
1238+
NVPTX::LD_GLOBAL_NC_v4i32, NVPTX::LD_GLOBAL_NC_v4i64);
12461239
break;
12471240
case NVPTXISD::LoadV8:
1248-
Opcode = pickOpcodeForVT(TargetVT, {/* no v8i8 */}, {/* no v8i16 */},
1241+
Opcode = pickOpcodeForVT(TargetVT, {/* no v8i16 */},
12491242
NVPTX::LD_GLOBAL_NC_v8i32, {/* no v8i64 */});
12501243
break;
12511244
}
@@ -1276,8 +1269,9 @@ bool NVPTXDAGToDAGISel::tryLDU(SDNode *N) {
12761269
break;
12771270
}
12781271

1279-
const MVT::SimpleValueType SelectVT =
1280-
MVT::getIntegerVT(LD->getMemoryVT().getSizeInBits() / NumElts).SimpleTy;
1272+
SDLoc DL(N);
1273+
const unsigned FromTypeWidth = LD->getMemoryVT().getSizeInBits() / NumElts;
1274+
const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
12811275

12821276
// If this is an LDU intrinsic, the address is the third operand. If its an
12831277
// LDU SD node (from custom vector handling), then its the second operand
@@ -1286,32 +1280,28 @@ bool NVPTXDAGToDAGISel::tryLDU(SDNode *N) {
12861280

12871281
SDValue Base, Offset;
12881282
SelectADDR(Addr, Base, Offset);
1289-
SDValue Ops[] = {Base, Offset, LD->getChain()};
1283+
SDValue Ops[] = {getI32Imm(FromTypeWidth, DL), Base, Offset, LD->getChain()};
12901284

12911285
std::optional<unsigned> Opcode;
12921286
switch (N->getOpcode()) {
12931287
default:
12941288
llvm_unreachable("Unexpected opcode");
12951289
case ISD::INTRINSIC_W_CHAIN:
1296-
Opcode =
1297-
pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_i8, NVPTX::LDU_GLOBAL_i16,
1298-
NVPTX::LDU_GLOBAL_i32, NVPTX::LDU_GLOBAL_i64);
1290+
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_i16,
1291+
NVPTX::LDU_GLOBAL_i32, NVPTX::LDU_GLOBAL_i64);
12991292
break;
13001293
case NVPTXISD::LDUV2:
1301-
Opcode = pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_v2i8,
1302-
NVPTX::LDU_GLOBAL_v2i16, NVPTX::LDU_GLOBAL_v2i32,
1303-
NVPTX::LDU_GLOBAL_v2i64);
1294+
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_v2i16,
1295+
NVPTX::LDU_GLOBAL_v2i32, NVPTX::LDU_GLOBAL_v2i64);
13041296
break;
13051297
case NVPTXISD::LDUV4:
1306-
Opcode = pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_v4i8,
1307-
NVPTX::LDU_GLOBAL_v4i16, NVPTX::LDU_GLOBAL_v4i32,
1308-
{/* no v4i64 */});
1298+
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_v4i16,
1299+
NVPTX::LDU_GLOBAL_v4i32, {/* no v4i64 */});
13091300
break;
13101301
}
13111302
if (!Opcode)
13121303
return false;
13131304

1314-
SDLoc DL(N);
13151305
SDNode *NVPTXLDU = CurDAG->getMachineNode(*Opcode, DL, LD->getVTList(), Ops);
13161306

13171307
ReplaceNode(LD, NVPTXLDU);
@@ -1362,8 +1352,8 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
13621352
Chain};
13631353

13641354
const std::optional<unsigned> Opcode =
1365-
pickOpcodeForVT(Value.getSimpleValueType().SimpleTy, NVPTX::ST_i8,
1366-
NVPTX::ST_i16, NVPTX::ST_i32, NVPTX::ST_i64);
1355+
pickOpcodeForVT(Value.getSimpleValueType().SimpleTy, NVPTX::ST_i16,
1356+
NVPTX::ST_i32, NVPTX::ST_i64);
13671357
if (!Opcode)
13681358
return false;
13691359

@@ -1423,16 +1413,16 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
14231413
default:
14241414
return false;
14251415
case NVPTXISD::StoreV2:
1426-
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i8_v2, NVPTX::STV_i16_v2,
1427-
NVPTX::STV_i32_v2, NVPTX::STV_i64_v2);
1416+
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i16_v2, NVPTX::STV_i32_v2,
1417+
NVPTX::STV_i64_v2);
14281418
break;
14291419
case NVPTXISD::StoreV4:
1430-
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i8_v4, NVPTX::STV_i16_v4,
1431-
NVPTX::STV_i32_v4, NVPTX::STV_i64_v4);
1420+
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i16_v4, NVPTX::STV_i32_v4,
1421+
NVPTX::STV_i64_v4);
14321422
break;
14331423
case NVPTXISD::StoreV8:
1434-
Opcode = pickOpcodeForVT(EltVT, {/* no v8i8 */}, {/* no v8i16 */},
1435-
NVPTX::STV_i32_v8, {/* no v8i64 */});
1424+
Opcode = pickOpcodeForVT(EltVT, {/* no v8i16 */}, NVPTX::STV_i32_v8,
1425+
{/* no v8i64 */});
14361426
break;
14371427
}
14381428

@@ -1687,10 +1677,11 @@ bool NVPTXDAGToDAGISel::tryBF16ArithToFMA(SDNode *N) {
16871677
auto API = APF.bitcastToAPInt();
16881678
API = API.concat(API);
16891679
auto Const = CurDAG->getTargetConstant(API, DL, MVT::i32);
1690-
return SDValue(CurDAG->getMachineNode(NVPTX::IMOV32i, DL, VT, Const), 0);
1680+
return SDValue(CurDAG->getMachineNode(NVPTX::MOV_B32_i, DL, VT, Const),
1681+
0);
16911682
}
16921683
auto Const = CurDAG->getTargetConstantFP(APF, DL, VT);
1693-
return SDValue(CurDAG->getMachineNode(NVPTX::BFMOV16i, DL, VT, Const), 0);
1684+
return SDValue(CurDAG->getMachineNode(NVPTX::MOV_BF16_i, DL, VT, Const), 0);
16941685
};
16951686

16961687
switch (N->getOpcode()) {

‎llvm/lib/Target/NVPTX/NVPTXInstrFormats.td

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,9 @@
1111
//
1212
//===----------------------------------------------------------------------===//
1313

14-
// Vector instruction type enum
15-
class VecInstTypeEnum<bits<4> val> {
16-
bits<4> Value=val;
17-
}
18-
def VecNOP : VecInstTypeEnum<0>;
19-
2014
// Generic NVPTX Format
2115

22-
class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
16+
class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
2317
: Instruction {
2418
field bits<14> Inst;
2519

@@ -30,7 +24,6 @@ class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
3024
let Pattern = pattern;
3125

3226
// TSFlagFields
33-
bits<4> VecInstType = VecNOP.Value;
3427
bit IsLoad = false;
3528
bit IsStore = false;
3629

@@ -45,7 +38,6 @@ class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
4538
// 2**(2-1) = 2.
4639
bits<2> IsSuld = 0;
4740

48-
let TSFlags{3...0} = VecInstType;
4941
let TSFlags{4} = IsLoad;
5042
let TSFlags{5} = IsStore;
5143
let TSFlags{6} = IsTex;

‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -35,23 +35,23 @@ void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3535
const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
3636
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
3737

38-
if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
38+
if (DestRC != SrcRC)
3939
report_fatal_error("Copy one register into another with a different width");
4040

4141
unsigned Op;
42-
if (DestRC == &NVPTX::B1RegClass) {
43-
Op = NVPTX::IMOV1r;
44-
} else if (DestRC == &NVPTX::B16RegClass) {
45-
Op = NVPTX::MOV16r;
46-
} else if (DestRC == &NVPTX::B32RegClass) {
47-
Op = NVPTX::IMOV32r;
48-
} else if (DestRC == &NVPTX::B64RegClass) {
49-
Op = NVPTX::IMOV64r;
50-
} else if (DestRC == &NVPTX::B128RegClass) {
51-
Op = NVPTX::IMOV128r;
52-
} else {
42+
if (DestRC == &NVPTX::B1RegClass)
43+
Op = NVPTX::MOV_B1_r;
44+
else if (DestRC == &NVPTX::B16RegClass)
45+
Op = NVPTX::MOV_B16_r;
46+
else if (DestRC == &NVPTX::B32RegClass)
47+
Op = NVPTX::MOV_B32_r;
48+
else if (DestRC == &NVPTX::B64RegClass)
49+
Op = NVPTX::MOV_B64_r;
50+
else if (DestRC == &NVPTX::B128RegClass)
51+
Op = NVPTX::MOV_B128_r;
52+
else
5353
llvm_unreachable("Bad register copy");
54-
}
54+
5555
BuildMI(MBB, I, DL, get(Op), DestReg)
5656
.addReg(SrcReg, getKillRegState(KillSrc));
5757
}

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