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[RISCV] add scmp RVV CodeGen tests
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scmp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define <16 x i8> @scmp_i8i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: scmp_i8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v9, v8
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v9
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %c
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}
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define <16 x i8> @scmp_z8i8(<16 x i8> %a) {
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; CHECK-LABEL: scmp_z8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <16 x i8> @llvm.scmp(<16 x i8> zeroinitializer, <16 x i8> %a)
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ret <16 x i8> %c
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}
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define <16 x i8> @scmp_i8z8(<16 x i8> %a) {
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; CHECK-LABEL: scmp_i8z8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> zeroinitializer)
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ret <16 x i8> %c
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}
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define <8 x i16> @scmp_i16i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: scmp_i16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v9, v8
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v9
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %c
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}
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define <8 x i16> @scmp_z16i16(<8 x i16> %a) {
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; CHECK-LABEL: scmp_z16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <8 x i16> @llvm.scmp(<8 x i16> zeroinitializer, <8 x i16> %a)
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ret <8 x i16> %c
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}
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define <8 x i16> @scmp_i16z16(<8 x i16> %a) {
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; CHECK-LABEL: scmp_i16z16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> zeroinitializer)
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ret <8 x i16> %c
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}
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define <4 x i32> @scmp_i32i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: scmp_i32i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v9, v8
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v9
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %c
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}
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define <4 x i32> @scmp_z32i32(<4 x i32> %a) {
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; CHECK-LABEL: scmp_z32i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <4 x i32> @llvm.scmp(<4 x i32> zeroinitializer, <4 x i32> %a)
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ret <4 x i32> %c
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}
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define <4 x i32> @scmp_i32z32(<4 x i32> %a) {
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; CHECK-LABEL: scmp_i32z32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> zeroinitializer)
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ret <4 x i32> %c
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}
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define <2 x i64> @scmp_i64i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: scmp_i64i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v9, v8
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v9
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %c
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}
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define <2 x i64> @scmp_z64i64(<2 x i64> %a) {
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; CHECK-LABEL: scmp_z64i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <2 x i64> @llvm.scmp(<2 x i64> zeroinitializer, <2 x i64> %a)
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ret <2 x i64> %c
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}
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define <2 x i64> @scmp_i64z64(<2 x i64> %a) {
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; CHECK-LABEL: scmp_i64z64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v9, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> zeroinitializer)
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ret <2 x i64> %c
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
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; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/scmp.ll

Lines changed: 206 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define <vscale x 16 x i8> @scmp_i8i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: scmp_i8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v10, v8
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v10
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; CHECK-NEXT: vmerge.vim v8, v12, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %c
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}
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define <vscale x 16 x i8> @scmp_z8i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: scmp_z8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vsrl.vi v8, v8, 7
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; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %c
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}
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define <vscale x 16 x i8> @scmp_i8z8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: scmp_i8z8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer)
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ret <vscale x 16 x i8> %c
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}
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define <vscale x 8 x i16> @scmp_i16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: scmp_i16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v10, v8
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v10
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; CHECK-NEXT: vmerge.vim v8, v12, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %c
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}
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define <vscale x 8 x i16> @scmp_z16i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: scmp_z16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vsrl.vi v8, v8, 15
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; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %a)
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ret <vscale x 8 x i16> %c
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}
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define <vscale x 8 x i16> @scmp_i16z16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: scmp_i16z16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vmsgt.vi v0, v8, 0
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmsle.vi v0, v8, -1
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer)
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ret <vscale x 8 x i16> %c
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}
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define <vscale x 4 x i32> @scmp_i32i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
94+
; CHECK-LABEL: scmp_i32i32:
95+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmslt.vv v0, v10, v8
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; CHECK-NEXT: vmv.v.i v12, 0
99+
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: vmslt.vv v0, v8, v10
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; CHECK-NEXT: vmerge.vim v8, v12, -1, v0
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; CHECK-NEXT: ret
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entry:
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%c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
105+
ret <vscale x 4 x i32> %c
106+
}
107+
108+
define <vscale x 4 x i32> @scmp_z32i32(<vscale x 4 x i32> %a) {
109+
; CHECK-LABEL: scmp_z32i32:
110+
; CHECK: # %bb.0: # %entry
111+
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
112+
; CHECK-NEXT: vmsgt.vi v0, v8, 0
113+
; CHECK-NEXT: vsrl.vi v8, v8, 31
114+
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
115+
; CHECK-NEXT: ret
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entry:
117+
%c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %a)
118+
ret <vscale x 4 x i32> %c
119+
}
120+
121+
define <vscale x 4 x i32> @scmp_i32z32(<vscale x 4 x i32> %a) {
122+
; RV32-LABEL: scmp_i32z32:
123+
; RV32: # %bb.0: # %entry
124+
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, mu
125+
; RV32-NEXT: vmsgt.vi v0, v8, 0
126+
; RV32-NEXT: vsra.vi v8, v8, 31
127+
; RV32-NEXT: vor.vi v8, v8, 1, v0.t
128+
; RV32-NEXT: ret
129+
;
130+
; RV64-LABEL: scmp_i32z32:
131+
; RV64: # %bb.0: # %entry
132+
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
133+
; RV64-NEXT: vmsgt.vi v0, v8, 0
134+
; RV64-NEXT: vmv.v.i v10, 0
135+
; RV64-NEXT: vmerge.vim v10, v10, 1, v0
136+
; RV64-NEXT: vmsle.vi v0, v8, -1
137+
; RV64-NEXT: vmerge.vim v8, v10, -1, v0
138+
; RV64-NEXT: ret
139+
entry:
140+
%c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer)
141+
ret <vscale x 4 x i32> %c
142+
}
143+
144+
145+
define <vscale x 2 x i64> @scmp_i64i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
146+
; CHECK-LABEL: scmp_i64i64:
147+
; CHECK: # %bb.0: # %entry
148+
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
149+
; CHECK-NEXT: vmslt.vv v0, v10, v8
150+
; CHECK-NEXT: vmv.v.i v12, 0
151+
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
152+
; CHECK-NEXT: vmslt.vv v0, v8, v10
153+
; CHECK-NEXT: vmerge.vim v8, v12, -1, v0
154+
; CHECK-NEXT: ret
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entry:
156+
%c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
157+
ret <vscale x 2 x i64> %c
158+
}
159+
160+
define <vscale x 2 x i64> @scmp_z64i64(<vscale x 2 x i64> %a) {
161+
; RV32-LABEL: scmp_z64i64:
162+
; RV32: # %bb.0: # %entry
163+
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
164+
; RV32-NEXT: vmsle.vi v0, v8, -1
165+
; RV32-NEXT: vmv.v.i v10, 0
166+
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
167+
; RV32-NEXT: vmsgt.vi v0, v8, 0
168+
; RV32-NEXT: vmerge.vim v8, v10, -1, v0
169+
; RV32-NEXT: ret
170+
;
171+
; RV64-LABEL: scmp_z64i64:
172+
; RV64: # %bb.0: # %entry
173+
; RV64-NEXT: li a0, 63
174+
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
175+
; RV64-NEXT: vmsgt.vi v0, v8, 0
176+
; RV64-NEXT: vsrl.vx v8, v8, a0
177+
; RV64-NEXT: vmerge.vim v8, v8, -1, v0
178+
; RV64-NEXT: ret
179+
entry:
180+
%c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %a)
181+
ret <vscale x 2 x i64> %c
182+
}
183+
184+
define <vscale x 2 x i64> @scmp_i64z64(<vscale x 2 x i64> %a) {
185+
; RV32-LABEL: scmp_i64z64:
186+
; RV32: # %bb.0: # %entry
187+
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
188+
; RV32-NEXT: vmsgt.vi v0, v8, 0
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; RV32-NEXT: vmv.v.i v10, 0
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; RV32-NEXT: vmerge.vim v10, v10, 1, v0
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; RV32-NEXT: vmsle.vi v0, v8, -1
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; RV32-NEXT: vmerge.vim v8, v10, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: scmp_i64z64:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: li a0, 63
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; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu
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; RV64-NEXT: vmsgt.vi v0, v8, 0
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; RV64-NEXT: vsra.vx v8, v8, a0
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; RV64-NEXT: vor.vi v8, v8, 1, v0.t
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; RV64-NEXT: ret
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entry:
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%c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer)
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ret <vscale x 2 x i64> %c
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}

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