[SLP] Fix a check for main/alternate interchanged instruction

If the instruction is checked for matching the main instruction, need to
check if the opcode of the main instruction is compatible with the
operands of the instruction. If they are not, need to check the
alternate instruction and its operands for compatibility and return
alternate instruction as a match.

Fixes #151699

Fixed check for non-supported binary operations.

Author: alexey-bataev

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -991,6 +991,17 @@ class BinOpSameOpcodeHelper {
         return Candidate & OrBIT;
       case Instruction::Xor:
         return Candidate & XorBIT;
+      case Instruction::LShr:
+      case Instruction::FAdd:
+      case Instruction::FSub:
+      case Instruction::FMul:
+      case Instruction::SDiv:
+      case Instruction::UDiv:
+      case Instruction::FDiv:
+      case Instruction::SRem:
+      case Instruction::URem:
+      case Instruction::FRem:
+        return false;
       default:
         break;
       }
@@ -1238,6 +1249,12 @@ class InstructionsState {
     BinOpSameOpcodeHelper Converter(MainOp);
     if (!Converter.add(I) || !Converter.add(MainOp))
       return nullptr;
+    if (isAltShuffle() && !Converter.hasCandidateOpcode(MainOp->getOpcode())) {
+      BinOpSameOpcodeHelper AltConverter(AltOp);
+      if (AltConverter.add(I) && AltConverter.add(AltOp) &&
+          AltConverter.hasCandidateOpcode(AltOp->getOpcode()))
+        return AltOp;
+    }
     if (Converter.hasAltOp() && !isAltShuffle())
       return nullptr;
     return Converter.hasAltOp() ? AltOp : MainOp;

llvm/test/Transforms/SLPVectorizer/X86/main-alternate-interechanged-detect.ll

@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define i64 @test() {
+; CHECK-LABEL: define i64 @test() {
+; CHECK-NEXT:  [[BB:.*]]:
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 0, 1
+; CHECK-NEXT:    [[ADD1:%.*]] = add i32 0, 1
+; CHECK-NEXT:    br label %[[BB2:.*]]
+; CHECK:       [[BB2]]:
+; CHECK-NEXT:    [[PHI:%.*]] = phi i32 [ [[SHL]], %[[BB]] ]
+; CHECK-NEXT:    [[PHI3:%.*]] = phi i32 [ 0, %[[BB]] ]
+; CHECK-NEXT:    [[PHI4:%.*]] = phi i32 [ 0, %[[BB]] ]
+; CHECK-NEXT:    [[PHI5:%.*]] = phi i32 [ [[ADD1]], %[[BB]] ]
+; CHECK-NEXT:    ret i64 0
+;
+bb:
+  %shl = shl i32 0, 1
+  %mul = mul i32 0, 0
+  %add = add i32 0, 0
+  %add1 = add i32 0, 1
+  br label %bb2
+
+bb2:
+  %phi = phi i32 [ %shl, %bb ]
+  %phi3 = phi i32 [ %add, %bb ]
+  %phi4 = phi i32 [ %mul, %bb ]
+  %phi5 = phi i32 [ %add1, %bb ]
+  ret i64 0
+}