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[AMDGPU][GlobalISel] Combine (or s64, zext(s32))
1 parent 205b401 commit f7c71a3

15 files changed

+691
-907
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,19 @@ def zext_of_shift_amount_combines : GICombineGroup<[
151151
canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
152152
]>;
153153

154+
// (or i64:x, (zext i32:y)) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
155+
// (or (zext i32:y), i64:x) -> i64:(merge (or lo_32(x), i32:y), hi_32(x))
156+
def or_s64_zext_s32_frag : GICombinePatFrag<(outs root:$dst), (ins $src_s64, $src_s32),
157+
[ (pattern (G_OR $dst, i64:$src_s64, i64:$zext_val), (G_ZEXT i64:$zext_val, i32:$src_s32)),
158+
(pattern (G_OR $dst, i64:$zext_val, i64:$src_s64), (G_ZEXT i64:$zext_val, i32:$src_s32))]>;
159+
160+
def combine_or_s64_s32 : GICombineRule<
161+
(defs root:$dst),
162+
(match (or_s64_zext_s32_frag $dst, i64:$x, i32:$y):$dst),
163+
(apply (G_UNMERGE_VALUES $x_lo, $x_hi, $x),
164+
(G_OR $or, $x_lo, $y),
165+
(G_MERGE_VALUES $dst, $or, $x_hi))>;
166+
154167
let Predicates = [Has16BitInsts, NotHasMed3_16] in {
155168
// For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
156169
// saves one instruction compared to the promotion.
@@ -180,15 +193,16 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
180193
def AMDGPUPreLegalizerCombiner: GICombiner<
181194
"AMDGPUPreLegalizerCombinerImpl",
182195
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
183-
foldable_fneg, combine_shuffle_vector_to_build_vector]> {
196+
foldable_fneg, combine_shuffle_vector_to_build_vector, combine_or_s64_s32]> {
184197
let CombineAllMethodName = "tryCombineAllImpl";
185198
}
186199

187200
def AMDGPUPostLegalizerCombiner: GICombiner<
188201
"AMDGPUPostLegalizerCombinerImpl",
189202
[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
190203
uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
191-
rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64]> {
204+
rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
205+
combine_or_s64_s32]> {
192206
let CombineAllMethodName = "tryCombineAllImpl";
193207
}
194208

‎llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1778,7 +1778,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
17781778
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
17791779
; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 31
17801780
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1781-
; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
1781+
; GFX6-NEXT: v_or_b32_e32 v0, v0, v3
17821782
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v2
17831783
; GFX6-NEXT: s_setpc_b64 s[30:31]
17841784
;
@@ -1790,7 +1790,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
17901790
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
17911791
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
17921792
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1793-
; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
1793+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
17941794
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v2
17951795
; GFX8-NEXT: s_setpc_b64 s[30:31]
17961796
;
@@ -1802,7 +1802,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
18021802
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
18031803
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
18041804
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v3
1805-
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
1805+
; GFX9-NEXT: v_or_b32_e32 v0, v0, v3
18061806
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v2
18071807
; GFX9-NEXT: s_setpc_b64 s[30:31]
18081808
;
@@ -1815,7 +1815,7 @@ define i65 @v_ashr_i65_33(i65 %value) {
18151815
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v1
18161816
; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]
18171817
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v2
1818-
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v3, v0
1818+
; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v3
18191819
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
18201820
%result = ashr i65 %value, 33
18211821
ret i65 %result
@@ -1875,21 +1875,19 @@ define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
18751875
; GCN-LABEL: s_ashr_i65_33:
18761876
; GCN: ; %bb.0:
18771877
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1878-
; GCN-NEXT: s_lshr_b32 s0, s1, 1
1879-
; GCN-NEXT: s_mov_b32 s1, 0
1880-
; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1881-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1878+
; GCN-NEXT: s_lshr_b32 s4, s1, 1
1879+
; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
1880+
; GCN-NEXT: s_or_b32 s0, s0, s4
18821881
; GCN-NEXT: s_ashr_i32 s2, s3, 1
18831882
; GCN-NEXT: ; return to shader part epilog
18841883
;
18851884
; GFX10PLUS-LABEL: s_ashr_i65_33:
18861885
; GFX10PLUS: ; %bb.0:
18871886
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1888-
; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1
1889-
; GFX10PLUS-NEXT: s_mov_b32 s1, 0
1890-
; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1887+
; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 1
1888+
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 31
18911889
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
1892-
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1890+
; GFX10PLUS-NEXT: s_or_b32 s0, s0, s4
18931891
; GFX10PLUS-NEXT: ; return to shader part epilog
18941892
%result = ashr i65 %value, 33
18951893
ret i65 %result

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,10 @@ body: |
1212
; CHECK-NEXT: {{ $}}
1313
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
1414
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
15-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
16-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ZEXT]]
17-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64)
15+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
16+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
17+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
18+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
1819
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
1920
%0:_(s64) = COPY $sgpr0_sgpr1
2021
%1:_(s32) = COPY $sgpr2
@@ -34,9 +35,10 @@ body: |
3435
; CHECK-NEXT: {{ $}}
3536
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
3637
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
37-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
38-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[COPY]]
39-
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[OR]](s64)
38+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
39+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
40+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
41+
; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
4042
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
4143
%0:_(s64) = COPY $sgpr0_sgpr1
4244
%1:_(s32) = COPY $sgpr2
@@ -57,12 +59,9 @@ body: |
5759
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
5860
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
5961
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
60-
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
61-
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
62-
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[MV]], [[ZEXT]]
63-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](s64)
64-
; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32)
65-
; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32)
62+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY2]]
63+
; CHECK-NEXT: $sgpr0 = COPY [[OR]](s32)
64+
; CHECK-NEXT: $sgpr1 = COPY [[COPY1]](s32)
6665
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
6766
%0:_(s32) = COPY $sgpr0
6867
%1:_(s32) = COPY $sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -230,30 +230,30 @@ define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3
230230
; GFX10-NEXT: s_mov_b32 s6, 0
231231
; GFX10-NEXT: s_getpc_b64 s[4:5]
232232
; GFX10-NEXT: s_mov_b32 s7, -1
233-
; GFX10-NEXT: s_mov_b32 s2, s1
233+
; GFX10-NEXT: s_mov_b32 s2, s0
234234
; GFX10-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
235-
; GFX10-NEXT: s_mov_b32 s1, 0
236235
; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0
237-
; GFX10-NEXT: s_or_b64 s[12:13], s[4:5], s[0:1]
238-
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[12:13], 0x0
236+
; GFX10-NEXT: s_mov_b32 s3, s5
237+
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
239238
; GFX10-NEXT: v_mbcnt_hi_u32_b32 v1, -1, v1
240239
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1
241240
; GFX10-NEXT: v_and_b32_e32 v3, 1, v1
242241
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
243-
; GFX10-NEXT: s_xor_b32 s3, vcc_lo, exec_lo
242+
; GFX10-NEXT: s_xor_b32 s2, vcc_lo, exec_lo
244243
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
245244
; GFX10-NEXT: buffer_load_dword v2, v2, s[4:7], 0 offen
246-
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s3
245+
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
246+
; GFX10-NEXT: s_mov_b32 s2, 0
247247
; GFX10-NEXT: s_waitcnt vmcnt(0)
248248
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v2
249249
; GFX10-NEXT: s_cbranch_vccnz .LBB4_4
250250
; GFX10-NEXT: ; %bb.1: ; %.preheader.preheader
251251
; GFX10-NEXT: s_mov_b32 s3, 0
252252
; GFX10-NEXT: .LBB4_2: ; %.preheader
253253
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
254-
; GFX10-NEXT: v_mov_b32_e32 v3, s1
254+
; GFX10-NEXT: v_mov_b32_e32 v3, s2
255255
; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1
256-
; GFX10-NEXT: s_add_i32 s1, s1, 4
256+
; GFX10-NEXT: s_add_i32 s2, s2, 4
257257
; GFX10-NEXT: buffer_load_dword v3, v3, s[4:7], 0 offen
258258
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
259259
; GFX10-NEXT: s_waitcnt vmcnt(0)
@@ -262,19 +262,19 @@ define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3
262262
; GFX10-NEXT: s_cbranch_vccnz .LBB4_2
263263
; GFX10-NEXT: ; %bb.3: ; %.preheader._crit_edge
264264
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v2
265-
; GFX10-NEXT: s_or_b32 s1, s0, vcc_lo
266-
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
265+
; GFX10-NEXT: s_or_b32 s2, s0, vcc_lo
266+
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2
267267
; GFX10-NEXT: s_branch .LBB4_6
268268
; GFX10-NEXT: .LBB4_4:
269-
; GFX10-NEXT: s_mov_b32 s1, exec_lo
269+
; GFX10-NEXT: s_mov_b32 s2, exec_lo
270270
; GFX10-NEXT: ; implicit-def: $vgpr1
271-
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s1
271+
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, s2
272272
; GFX10-NEXT: s_cbranch_vccz .LBB4_6
273273
; GFX10-NEXT: ; %bb.5: ; %.19
274274
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
275275
; GFX10-NEXT: v_or_b32_e32 v1, 2, v1
276276
; GFX10-NEXT: .LBB4_6: ; %.22
277-
; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, 2
277+
; GFX10-NEXT: v_add_lshl_u32 v0, v0, s1, 2
278278
; GFX10-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
279279
; GFX10-NEXT: s_endpgm
280280
.entry:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

Lines changed: 27 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -4959,17 +4959,15 @@ define amdgpu_ps i64 @s_fshl_i64_5(i64 inreg %lhs, i64 inreg %rhs) {
49594959
; GCN: ; %bb.0:
49604960
; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
49614961
; GCN-NEXT: s_lshr_b32 s2, s3, 27
4962-
; GCN-NEXT: s_mov_b32 s3, 0
4963-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4962+
; GCN-NEXT: s_or_b32 s0, s0, s2
49644963
; GCN-NEXT: ; return to shader part epilog
49654964
;
49664965
; GFX11-LABEL: s_fshl_i64_5:
49674966
; GFX11: ; %bb.0:
49684967
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 5
49694968
; GFX11-NEXT: s_lshr_b32 s2, s3, 27
4970-
; GFX11-NEXT: s_mov_b32 s3, 0
49714969
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
4972-
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4970+
; GFX11-NEXT: s_or_b32 s0, s0, s2
49734971
; GFX11-NEXT: ; return to shader part epilog
49744972
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 5)
49754973
ret i64 %result
@@ -4979,20 +4977,13 @@ define amdgpu_ps i64 @s_fshl_i64_32(i64 inreg %lhs, i64 inreg %rhs) {
49794977
; GCN-LABEL: s_fshl_i64_32:
49804978
; GCN: ; %bb.0:
49814979
; GCN-NEXT: s_mov_b32 s1, s0
4982-
; GCN-NEXT: s_mov_b32 s0, 0
4983-
; GCN-NEXT: s_mov_b32 s2, s3
4984-
; GCN-NEXT: s_mov_b32 s3, s0
4985-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4980+
; GCN-NEXT: s_mov_b32 s0, s3
49864981
; GCN-NEXT: ; return to shader part epilog
49874982
;
49884983
; GFX11-LABEL: s_fshl_i64_32:
49894984
; GFX11: ; %bb.0:
49904985
; GFX11-NEXT: s_mov_b32 s1, s0
4991-
; GFX11-NEXT: s_mov_b32 s0, 0
4992-
; GFX11-NEXT: s_mov_b32 s2, s3
4993-
; GFX11-NEXT: s_mov_b32 s3, s0
4994-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
4995-
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
4986+
; GFX11-NEXT: s_mov_b32 s0, s3
49964987
; GFX11-NEXT: ; return to shader part epilog
49974988
%result = call i64 @llvm.fshl.i64(i64 %lhs, i64 %rhs, i64 32)
49984989
ret i64 %result
@@ -6877,56 +6868,50 @@ define amdgpu_ps i128 @s_fshl_i128_65(i128 inreg %lhs, i128 inreg %rhs) {
68776868
; GFX6: ; %bb.0:
68786869
; GFX6-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
68796870
; GFX6-NEXT: s_lshr_b32 s4, s5, 31
6880-
; GFX6-NEXT: s_mov_b32 s5, 0
68816871
; GFX6-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6882-
; GFX6-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6872+
; GFX6-NEXT: s_or_b32 s0, s0, s4
68836873
; GFX6-NEXT: s_lshr_b32 s4, s7, 31
6884-
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6874+
; GFX6-NEXT: s_or_b32 s2, s2, s4
68856875
; GFX6-NEXT: ; return to shader part epilog
68866876
;
68876877
; GFX8-LABEL: s_fshl_i128_65:
68886878
; GFX8: ; %bb.0:
68896879
; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
68906880
; GFX8-NEXT: s_lshr_b32 s4, s5, 31
6891-
; GFX8-NEXT: s_mov_b32 s5, 0
68926881
; GFX8-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6893-
; GFX8-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6882+
; GFX8-NEXT: s_or_b32 s0, s0, s4
68946883
; GFX8-NEXT: s_lshr_b32 s4, s7, 31
6895-
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6884+
; GFX8-NEXT: s_or_b32 s2, s2, s4
68966885
; GFX8-NEXT: ; return to shader part epilog
68976886
;
68986887
; GFX9-LABEL: s_fshl_i128_65:
68996888
; GFX9: ; %bb.0:
69006889
; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
69016890
; GFX9-NEXT: s_lshr_b32 s4, s5, 31
6902-
; GFX9-NEXT: s_mov_b32 s5, 0
69036891
; GFX9-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6904-
; GFX9-NEXT: s_or_b64 s[0:1], s[4:5], s[0:1]
6892+
; GFX9-NEXT: s_or_b32 s0, s0, s4
69056893
; GFX9-NEXT: s_lshr_b32 s4, s7, 31
6906-
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
6894+
; GFX9-NEXT: s_or_b32 s2, s2, s4
69076895
; GFX9-NEXT: ; return to shader part epilog
69086896
;
69096897
; GFX10-LABEL: s_fshl_i128_65:
69106898
; GFX10: ; %bb.0:
6911-
; GFX10-NEXT: s_lshr_b32 s2, s5, 31
6912-
; GFX10-NEXT: s_mov_b32 s3, 0
6913-
; GFX10-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
6914-
; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
6915-
; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
6916-
; GFX10-NEXT: s_lshr_b32 s2, s7, 31
6917-
; GFX10-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
6899+
; GFX10-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
6900+
; GFX10-NEXT: s_lshr_b32 s4, s5, 31
6901+
; GFX10-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6902+
; GFX10-NEXT: s_lshr_b32 s5, s7, 31
6903+
; GFX10-NEXT: s_or_b32 s0, s0, s4
6904+
; GFX10-NEXT: s_or_b32 s2, s2, s5
69186905
; GFX10-NEXT: ; return to shader part epilog
69196906
;
69206907
; GFX11-LABEL: s_fshl_i128_65:
69216908
; GFX11: ; %bb.0:
6922-
; GFX11-NEXT: s_lshr_b32 s2, s5, 31
6923-
; GFX11-NEXT: s_mov_b32 s3, 0
6924-
; GFX11-NEXT: s_lshl_b64 s[4:5], s[6:7], 1
6925-
; GFX11-NEXT: s_lshl_b64 s[8:9], s[0:1], 1
6926-
; GFX11-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
6927-
; GFX11-NEXT: s_lshr_b32 s2, s7, 31
6928-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
6929-
; GFX11-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
6909+
; GFX11-NEXT: s_lshl_b64 s[2:3], s[0:1], 1
6910+
; GFX11-NEXT: s_lshr_b32 s4, s5, 31
6911+
; GFX11-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
6912+
; GFX11-NEXT: s_lshr_b32 s5, s7, 31
6913+
; GFX11-NEXT: s_or_b32 s0, s0, s4
6914+
; GFX11-NEXT: s_or_b32 s2, s2, s5
69306915
; GFX11-NEXT: ; return to shader part epilog
69316916
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)
69326917
ret i128 %result
@@ -6939,7 +6924,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69396924
; GFX6-NEXT: v_lshl_b64 v[2:3], v[0:1], 1
69406925
; GFX6-NEXT: v_lshl_b64 v[0:1], v[6:7], 1
69416926
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6942-
; GFX6-NEXT: v_or_b32_e32 v0, v4, v0
6927+
; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
69436928
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 31, v7
69446929
; GFX6-NEXT: v_or_b32_e32 v2, v2, v4
69456930
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -6950,7 +6935,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69506935
; GFX8-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
69516936
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
69526937
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6953-
; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
6938+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
69546939
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 31, v7
69556940
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
69566941
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -6961,7 +6946,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69616946
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
69626947
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
69636948
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v5
6964-
; GFX9-NEXT: v_or_b32_e32 v0, v4, v0
6949+
; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
69656950
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v7
69666951
; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
69676952
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -6973,7 +6958,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69736958
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 1, v[6:7]
69746959
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 31, v5
69756960
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 31, v7
6976-
; GFX10-NEXT: v_or_b32_e32 v0, v4, v0
6961+
; GFX10-NEXT: v_or_b32_e32 v0, v0, v4
69776962
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
69786963
; GFX10-NEXT: s_setpc_b64 s[30:31]
69796964
;
@@ -6985,7 +6970,7 @@ define i128 @v_fshl_i128_65(i128 %lhs, i128 %rhs) {
69856970
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 31, v5
69866971
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 31, v7
69876972
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
6988-
; GFX11-NEXT: v_or_b32_e32 v0, v4, v0
6973+
; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
69896974
; GFX11-NEXT: v_or_b32_e32 v2, v2, v5
69906975
; GFX11-NEXT: s_setpc_b64 s[30:31]
69916976
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 65)

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