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[AMDGPU] Add V_ASHR_PK_I8_I32 and V_ASHR_PK_U8_I32 on gfx1250
1 parent c8b6ddf commit f9d1665

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‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2013,6 +2013,8 @@ let AssemblerPredicate = isGFX11Plus in {
20132013

20142014
// These instructions differ from GFX12 variant by supporting DPP:
20152015
defm V_LSHL_ADD_U64 : VOP3Only_Realtriple_gfx1250<0x252>;
2016+
defm V_ASHR_PK_I8_I32 : VOP3Only_Realtriple_gfx1250<0x290>;
2017+
defm V_ASHR_PK_U8_I32 : VOP3Only_Realtriple_gfx1250<0x291>;
20162018
defm V_CVT_PK_BF16_F32 : VOP3Only_Realtriple_gfx1250<0x36d>;
20172019
defm V_CVT_SR_PK_BF16_F32 : VOP3Only_Realtriple_gfx1250<0x36e>;
20182020

‎llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s
34
define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
45
; GFX950-LABEL: v_ashr_pk_i8_i32:
56
; GFX950: ; %bb.0:
@@ -13,6 +14,20 @@ define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i3
1314
; GFX950-NEXT: v_ashr_pk_i8_i32 v1, s0, v1, v2
1415
; GFX950-NEXT: global_store_short v0, v1, s[6:7]
1516
; GFX950-NEXT: s_endpgm
17+
;
18+
; GFX1250-LABEL: v_ashr_pk_i8_i32:
19+
; GFX1250: ; %bb.0:
20+
; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
21+
; GFX1250-NEXT: s_wait_xcnt 0x0
22+
; GFX1250-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
23+
; GFX1250-NEXT: v_mov_b32_e32 v1, 0
24+
; GFX1250-NEXT: s_wait_kmcnt 0x0
25+
; GFX1250-NEXT: s_and_b32 s2, s2, 31
26+
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
27+
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
28+
; GFX1250-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v0
29+
; GFX1250-NEXT: global_store_b16 v1, v0, s[4:5]
30+
; GFX1250-NEXT: s_endpgm
1631
%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
1732
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
1833
%src2.clamp = and i32 %src2, 31
@@ -40,6 +55,20 @@ define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i3
4055
; GFX950-NEXT: v_ashr_pk_u8_i32 v1, s0, v1, v2
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; GFX950-NEXT: global_store_short v0, v1, s[6:7]
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; GFX950-NEXT: s_endpgm
58+
;
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; GFX1250-LABEL: v_ashr_pk_u8_i32:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
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; GFX1250-NEXT: s_wait_xcnt 0x0
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; GFX1250-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
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; GFX1250-NEXT: v_mov_b32_e32 v1, 0
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; GFX1250-NEXT: s_wait_kmcnt 0x0
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; GFX1250-NEXT: s_and_b32 s2, s2, 31
67+
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX1250-NEXT: v_mov_b32_e32 v0, s2
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; GFX1250-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v0
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; GFX1250-NEXT: global_store_b16 v1, v0, s[4:5]
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; GFX1250-NEXT: s_endpgm
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%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
4473
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
4574
%src2.clamp = and i32 %src2, 31

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3-fake16.s

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -366,3 +366,39 @@ v_cvt_sr_pk_bf16_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
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367367
v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
368368
// GFX1250: v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6e,0xd7,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
369+
370+
v_ashr_pk_i8_i32 v2, s4, v7, v8
371+
// GFX1250: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
372+
373+
v_ashr_pk_i8_i32 v2, v4, 0, 1
374+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
375+
376+
v_ashr_pk_i8_i32 v2, v4, 3, s2
377+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
378+
379+
v_ashr_pk_i8_i32 v2, s4, 4, v2
380+
// GFX1250: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
381+
382+
v_ashr_pk_i8_i32 v2, v4, v7, 12345
383+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
384+
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v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
386+
// GFX1250: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
387+
388+
v_ashr_pk_u8_i32 v2, s4, v7, v8
389+
// GFX1250: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
390+
391+
v_ashr_pk_u8_i32 v2, v4, 0, 1
392+
// GFX1250: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
393+
394+
v_ashr_pk_u8_i32 v2, v4, 3, s2
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// GFX1250: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
396+
397+
v_ashr_pk_u8_i32 v2, s4, 4, v2
398+
// GFX1250: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
399+
400+
v_ashr_pk_u8_i32 v2, v4, v7, 12345
401+
// GFX1250: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
402+
403+
v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
404+
// GFX1250: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3.s

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -366,3 +366,39 @@ v_cvt_sr_pk_bf16_f32 v5, -src_scc, |vcc_lo|, -1 mul:4
366366

367367
v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2
368368
// GFX1250: v_cvt_sr_pk_bf16_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6e,0xd7,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf]
369+
370+
v_ashr_pk_i8_i32 v2, s4, v7, v8
371+
// GFX1250: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
372+
373+
v_ashr_pk_i8_i32 v2, v4, 0, 1
374+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
375+
376+
v_ashr_pk_i8_i32 v2, v4, 3, s2
377+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
378+
379+
v_ashr_pk_i8_i32 v2, s4, 4, v2
380+
// GFX1250: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
381+
382+
v_ashr_pk_i8_i32 v2, v4, v7, 12345
383+
// GFX1250: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
384+
385+
v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
386+
// GFX1250: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
387+
388+
v_ashr_pk_u8_i32 v2, s4, v7, v8
389+
// GFX1250: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
390+
391+
v_ashr_pk_u8_i32 v2, v4, 0, 1
392+
// GFX1250: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
393+
394+
v_ashr_pk_u8_i32 v2, v4, 3, s2
395+
// GFX1250: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
396+
397+
v_ashr_pk_u8_i32 v2, s4, 4, v2
398+
// GFX1250: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
399+
400+
v_ashr_pk_u8_i32 v2, v4, v7, 12345
401+
// GFX1250: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
402+
403+
v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1]
404+
// GFX1250: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16-fake16.s

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,3 +297,35 @@ v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, -|v2|, 5 mul:4 row_xmask:0 row_mask:0x1 ban
297297
v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
298298
// GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x6e,0xd7,0xfa,0xfe,0xf7,0x7b,0xff,0x6f,0x05,0x30]
299299
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
300+
301+
v_ashr_pk_i8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
302+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
303+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
304+
305+
v_ashr_pk_i8_i32 v2, v4, v7, v8 row_share:3 fi:1
306+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
307+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
308+
309+
v_ashr_pk_i8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
310+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
311+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
312+
313+
v_ashr_pk_i8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
314+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
315+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
316+
317+
v_ashr_pk_u8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
318+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
319+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
320+
321+
v_ashr_pk_u8_i32 v2, v4, v7, v8 row_share:3 fi:1
322+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
323+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
324+
325+
v_ashr_pk_u8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
326+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
327+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
328+
329+
v_ashr_pk_u8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
330+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
331+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp16.s

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,3 +297,35 @@ v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, -|v2|, 5 mul:4 row_xmask:0 row_mask:0x1 ban
297297
v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
298298
// GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xff,0x83,0x6e,0xd7,0xfa,0xfe,0xf7,0x7b,0xff,0x6f,0x05,0x30]
299299
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
300+
301+
v_ashr_pk_i8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
302+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
303+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
304+
305+
v_ashr_pk_i8_i32 v2, v4, v7, v8 row_share:3 fi:1
306+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
307+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
308+
309+
v_ashr_pk_i8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
310+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
311+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
312+
313+
v_ashr_pk_i8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
314+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x90,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
315+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
316+
317+
v_ashr_pk_u8_i32 v2, v4, v7, v8 quad_perm:[1,2,3,1]
318+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 quad_perm:[1,2,3,1] row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x79,0x00,0xff]
319+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
320+
321+
v_ashr_pk_u8_i32 v2, v4, v7, v8 row_share:3 fi:1
322+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, v8 row_share:3 row_mask:0xf bank_mask:0xf fi:1 ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x22,0x04,0x04,0x53,0x05,0xff]
323+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
324+
325+
v_ashr_pk_u8_i32 v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf
326+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x02,0x00,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0xff]
327+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
328+
329+
v_ashr_pk_u8_i32 v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3
330+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v2, v4, v7, 1 op_sel:[0,0,0,1] row_share:0 row_mask:0x5 bank_mask:0x3 ; encoding: [0x02,0x40,0x91,0xd6,0xfa,0x0e,0x06,0x02,0x04,0x50,0x01,0x53]
331+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8-fake16.s

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,3 +209,19 @@ v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, -|v2|, 5 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
209209
v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
210210
// GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x6e,0xd7,0xe9,0xfe,0xf7,0x7b,0xff,0x00,0x00,0x00]
211211
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
212+
213+
v_ashr_pk_i8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
214+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
215+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
216+
217+
v_ashr_pk_i8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
218+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
219+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
220+
221+
v_ashr_pk_u8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
222+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
223+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
224+
225+
v_ashr_pk_u8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
226+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
227+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3_dpp8.s

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,3 +209,19 @@ v_cvt_sr_pk_bf16_f32_e64_dpp v5, v1, -|v2|, 5 mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1
209209
v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0
210210
// GFX1250: v_cvt_sr_pk_bf16_f32_e64_dpp v255, -|v255|, -|v255|, src_scc clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x83,0x6e,0xd7,0xe9,0xfe,0xf7,0x7b,0xff,0x00,0x00,0x00]
211211
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
212+
213+
v_ashr_pk_i8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
214+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x90,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
215+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
216+
217+
v_ashr_pk_i8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
218+
// GFX1250: v_ashr_pk_i8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x90,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
219+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
220+
221+
v_ashr_pk_u8_i32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0]
222+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x91,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05]
223+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU
224+
225+
v_ashr_pk_u8_i32 v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1
226+
// GFX1250: v_ashr_pk_u8_i32_e64_dpp v5, v1, v2, s3 op_sel:[0,0,0,1] dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x40,0x91,0xd6,0xea,0x04,0x0e,0x00,0x01,0x77,0x39,0x05]
227+
// GFX12-ERR: :[[@LINE-2]]:1: error: instruction not supported on this GPU

‎llvm/test/MC/AMDGPU/gfx1250_asm_vop3_err.s

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,3 +86,13 @@ v_mad_nc_i64_i32 v[4:5], v2, v5, v[6:7] quad_perm:[3,2,1,0]
8686
// GFX1251-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: DP ALU dpp only supports row_share
8787
// GFX125X-ERR-NEXT:{{^}}v_mad_nc_i64_i32 v[4:5], v2, v5, v[6:7] quad_perm:[3,2,1,0]
8888
// GFX125X-ERR-NEXT:{{^}} ^
89+
90+
v_ashr_pk_i8_i32 v1, v2, v3, v4 clamp
91+
// GFX125X-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
92+
// GFX125X-ERR-NEXT:{{^}}v_ashr_pk_i8_i32 v1, v2, v3, v4 clamp
93+
// GFX125X-ERR-NEXT:{{^}} ^
94+
95+
v_ashr_pk_u8_i32 v1, v2, v3, v4 clamp
96+
// GFX125X-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
97+
// GFX125X-ERR-NEXT:{{^}}v_ashr_pk_u8_i32 v1, v2, v3, v4 clamp
98+
// GFX125X-ERR-NEXT:{{^}} ^

‎llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3.txt

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,42 @@
386386
0x05,0x01,0x6e,0xd7,0x7e,0x82,0xad,0x01
387387
# GFX1250: v_cvt_sr_pk_bf16_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6e,0xd7,0x7e,0x82,0xad,0x01]
388388

389+
0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04
390+
# GFX1250: v_ashr_pk_i8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x08,0x09,0x04]
391+
392+
0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04
393+
# GFX1250: v_ashr_pk_i8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0e,0x22,0x04]
394+
395+
0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02
396+
# GFX1250: v_ashr_pk_i8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x01,0x05,0x02]
397+
398+
0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00
399+
# GFX1250: v_ashr_pk_i8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x07,0x09,0x00]
400+
401+
0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00
402+
# GFX1250: v_ashr_pk_i8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x90,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
403+
404+
0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04
405+
# GFX1250: v_ashr_pk_i8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x90,0xd6,0x02,0x07,0x12,0x04]
406+
407+
0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04
408+
# GFX1250: v_ashr_pk_u8_i32 v2, s4, 4, v2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x08,0x09,0x04]
409+
410+
0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04
411+
# GFX1250: v_ashr_pk_u8_i32 v2, s4, v7, v8 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0e,0x22,0x04]
412+
413+
0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02
414+
# GFX1250: v_ashr_pk_u8_i32 v2, v4, 0, 1 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x01,0x05,0x02]
415+
416+
0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00
417+
# GFX1250: v_ashr_pk_u8_i32 v2, v4, 3, s2 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x07,0x09,0x00]
418+
419+
0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00
420+
# GFX1250: v_ashr_pk_u8_i32 v2, v4, v7, 0x3039 ; encoding: [0x02,0x00,0x91,0xd6,0x04,0x0f,0xfe,0x03,0x39,0x30,0x00,0x00]
421+
422+
0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04
423+
# GFX1250: v_ashr_pk_u8_i32 v1, v2, v3, v4 op_sel:[0,0,0,1] ; encoding: [0x01,0x40,0x91,0xd6,0x02,0x07,0x12,0x04]
424+
389425
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
390426
# GFX1250-FAKE16: {{.*}}
391427
# GFX1250-REAL16: {{.*}}

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