From 268af9b541d27be7f6df5fac5fed1af7fe42bc86 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Tue, 1 Jul 2025 07:29:42 +0530 Subject: [PATCH 1/2] Pre-commit test --- llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll | 153 ++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll diff --git a/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll b/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll new file mode 100644 index 0000000000000..4dbe25b21cddf --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll @@ -0,0 +1,153 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s + +@.str = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, 3'RD STRING\00", align 1 +@.str1 = private unnamed_addr constant [3 x i8] c"%s\00", align 1 + +; Function Attrs: nounwind +declare i32 @printf(i8* nocapture readonly, ...) + +; Function Attrs: nounwind +define i32 @main() { +; CHECK-LABEL: main: +; CHECK: .cfi_startproc +; CHECK-NEXT: // %bb.0: // %entry +; CHECK-NEXT: { +; CHECK-NEXT: r1 = ##.L.str +; CHECK-NEXT: allocframe(#40) +; CHECK-NEXT: } +; CHECK-NEXT: .cfi_def_cfa r30, 8 +; CHECK-NEXT: .cfi_offset r31, -4 +; CHECK-NEXT: .cfi_offset r30, -8 +; CHECK-NEXT: { +; CHECK-NEXT: r0 = add(r29,#8) +; CHECK-NEXT: memw(r29+#0) = r0.new +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = memub(r1+#30) +; CHECK-NEXT: memb(r29+#38) = r0.new +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = ##.L.str1 +; CHECK-NEXT: r2 = memub(r1+#29) +; CHECK-NEXT: r3 = memub(r1+#28) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 |= asl(r2,#8) +; CHECK-NEXT: r4 = memub(r1+#27) +; CHECK-NEXT: memh(r29+#36) = r3.new +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 = asl(r4,#24) +; CHECK-NEXT: r2 = memub(r1+#26) +; CHECK-NEXT: r4 = memub(r1+#25) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 |= asl(r2,#16) +; CHECK-NEXT: r2 = asl(r4,#8) +; CHECK-NEXT: r5 = memub(r1+#24) +; CHECK-NEXT: r4 = memub(r1+#19) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 |= or(r2,r5) +; CHECK-NEXT: r2 = asl(r4,#24) +; CHECK-NEXT: r6 = memub(r1+#18) +; CHECK-NEXT: memw(r29+#32) = r3.new +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r2 |= asl(r6,#16) +; CHECK-NEXT: r3 = memub(r1+#17) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 = asl(r3,#8) +; CHECK-NEXT: r4 = memub(r1+#16) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r2 |= or(r3,r4) +; CHECK-NEXT: r3 = memub(r1+#23) +; CHECK-NEXT: r4 = memub(r1+#22) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 = asl(r3,#24) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r3 |= asl(r4,#16) +; CHECK-NEXT: r4 = memub(r1+#11) +; CHECK-NEXT: r5 = memub(r1+#21) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r4 = asl(r4,#24) +; CHECK-NEXT: r5 = asl(r5,#8) +; CHECK-NEXT: r6 = memub(r1+#10) +; CHECK-NEXT: r8 = memub(r1+#20) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r4 |= asl(r6,#16) +; CHECK-NEXT: r3 |= or(r5,r8) +; CHECK-NEXT: r7 = memub(r1+#9) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r6 = asl(r7,#8) +; CHECK-NEXT: r7 = memub(r1+#8) +; CHECK-NEXT: memd(r29+#24) = r3:2 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r4 |= or(r6,r7) +; CHECK-NEXT: r6 = memub(r1+#3) +; CHECK-NEXT: r5 = memub(r1+#15) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r6 = asl(r6,#24) +; CHECK-NEXT: r5 = asl(r5,#24) +; CHECK-NEXT: r7 = memub(r1+#2) +; CHECK-NEXT: r9 = memub(r1+#14) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r6 |= asl(r7,#16) +; CHECK-NEXT: r5 |= asl(r9,#16) +; CHECK-NEXT: r14 = memub(r1+#1) +; CHECK-NEXT: r28 = memub(r1+#13) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r7 = asl(r14,#8) +; CHECK-NEXT: r8 = asl(r28,#8) +; CHECK-NEXT: r15 = memub(r1+#0) +; CHECK-NEXT: r11 = memub(r1+#12) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r6 |= or(r7,r15) +; CHECK-NEXT: r5 |= or(r8,r11) +; CHECK-NEXT: r7 = memub(r1+#7) +; CHECK-NEXT: r10 = memub(r1+#6) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r7 = asl(r7,#24) +; CHECK-NEXT: r12 = memub(r1+#5) +; CHECK-NEXT: memd(r29+#16) = r5:4 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r7 |= asl(r10,#16) +; CHECK-NEXT: r12 = asl(r12,#8) +; CHECK-NEXT: r1 = memub(r1+#4) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r7 |= or(r12,r1) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: call printf +; CHECK-NEXT: memd(r29+#8) = r7:6 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r0 = #0 +; CHECK-NEXT: dealloc_return +; CHECK-NEXT: } +entry: + %blah = alloca [30 x i8], align 8 + %arraydecay = getelementptr inbounds [30 x i8], [30 x i8]* %blah, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %arraydecay, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str, i32 0, i32 0), i32 31, i32 1, i1 false) + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str1, i32 0, i32 0), i8* %arraydecay) + ret i32 0 +} + +; Function Attrs: nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) From da84fe47749caa61f573e77157589319dcacf083 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Tue, 1 Jul 2025 07:44:28 +0530 Subject: [PATCH 2/2] [Hexagon] Implement shouldConvertConstantLoadToIntImm This will convert loads of constant strings to immediate values. Put this behind a flag that is enabled by default so that we can toggle it if need be. --- .../Target/Hexagon/HexagonISelLowering.cpp | 16 +++ llvm/lib/Target/Hexagon/HexagonISelLowering.h | 5 + llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll | 118 ++---------------- 3 files changed, 32 insertions(+), 107 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 6534ae938fede..e7d0ec6ee0fe5 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -102,6 +102,10 @@ static cl::opt MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::init(4), cl::desc("Max #stores to inline memset")); +static cl::opt + ConstantLoadsToImm("constant-loads-to-imm", cl::Hidden, cl::init(true), + cl::desc("Convert constant loads to immediate values.")); + static cl::opt AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads")); @@ -3607,6 +3611,18 @@ bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, return true; } +/// Returns true if it is beneficial to convert a load of a constant +/// to just the constant itself. +bool HexagonTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, + Type *Ty) const { + if (!ConstantLoadsToImm) + return false; + + assert(Ty->isIntegerTy()); + unsigned BitSize = Ty->getPrimitiveSizeInBits(); + return (BitSize > 0 && BitSize <= 64); +} + /// isLegalAddressingMode - Return true if the addressing mode represented by /// AM is legal for this target, for a load/store of the specified type. bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL, diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 1321bee44a295..a2c9b57d04caa 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -342,6 +342,11 @@ class HexagonTargetLowering : public TargetLowering { SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override; + /// Returns true if it is beneficial to convert a load of a constant + /// to just the constant itself. + bool shouldConvertConstantLoadToIntImm(const APInt &Imm, + Type *Ty) const override; + bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional ByteOffset) const override; diff --git a/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll b/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll index 4dbe25b21cddf..b23366bc11aca 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon-strcpy.ll @@ -12,130 +12,34 @@ define i32 @main() { ; CHECK-LABEL: main: ; CHECK: .cfi_startproc ; CHECK-NEXT: // %bb.0: // %entry -; CHECK-NEXT: { -; CHECK-NEXT: r1 = ##.L.str -; CHECK-NEXT: allocframe(#40) -; CHECK-NEXT: } ; CHECK-NEXT: .cfi_def_cfa r30, 8 ; CHECK-NEXT: .cfi_offset r31, -4 ; CHECK-NEXT: .cfi_offset r30, -8 ; CHECK-NEXT: { -; CHECK-NEXT: r0 = add(r29,#8) -; CHECK-NEXT: memw(r29+#0) = r0.new -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r0 = memub(r1+#30) -; CHECK-NEXT: memb(r29+#38) = r0.new -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: r0 = ##.L.str1 -; CHECK-NEXT: r2 = memub(r1+#29) -; CHECK-NEXT: r3 = memub(r1+#28) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 |= asl(r2,#8) -; CHECK-NEXT: r4 = memub(r1+#27) -; CHECK-NEXT: memh(r29+#36) = r3.new -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 = asl(r4,#24) -; CHECK-NEXT: r2 = memub(r1+#26) -; CHECK-NEXT: r4 = memub(r1+#25) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 |= asl(r2,#16) -; CHECK-NEXT: r2 = asl(r4,#8) -; CHECK-NEXT: r5 = memub(r1+#24) -; CHECK-NEXT: r4 = memub(r1+#19) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 |= or(r2,r5) -; CHECK-NEXT: r2 = asl(r4,#24) -; CHECK-NEXT: r6 = memub(r1+#18) -; CHECK-NEXT: memw(r29+#32) = r3.new -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r2 |= asl(r6,#16) -; CHECK-NEXT: r3 = memub(r1+#17) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 = asl(r3,#8) -; CHECK-NEXT: r4 = memub(r1+#16) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r2 |= or(r3,r4) -; CHECK-NEXT: r3 = memub(r1+#23) -; CHECK-NEXT: r4 = memub(r1+#22) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 = asl(r3,#24) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r3 |= asl(r4,#16) -; CHECK-NEXT: r4 = memub(r1+#11) -; CHECK-NEXT: r5 = memub(r1+#21) +; CHECK-NEXT: r3:2 = CONST64(#2325073635944967245) +; CHECK-NEXT: allocframe(r29,#40):raw ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r4 = asl(r4,#24) -; CHECK-NEXT: r5 = asl(r5,#8) -; CHECK-NEXT: r6 = memub(r1+#10) -; CHECK-NEXT: r8 = memub(r1+#20) +; CHECK-NEXT: r1 = add(r29,#8) +; CHECK-NEXT: r7:6 = CONST64(#4706902966564560965) +; CHECK-NEXT: r5:4 = CONST64(#5642821575076104260) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r4 |= asl(r6,#16) -; CHECK-NEXT: r3 |= or(r5,r8) -; CHECK-NEXT: r7 = memub(r1+#9) +; CHECK-NEXT: memb(r29+#38) = #0 +; CHECK-NEXT: memw(r29+#0) = r1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r6 = asl(r7,#8) -; CHECK-NEXT: r7 = memub(r1+#8) ; CHECK-NEXT: memd(r29+#24) = r3:2 +; CHECK-NEXT: memd(r29+#16) = r7:6 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r4 |= or(r6,r7) -; CHECK-NEXT: r6 = memub(r1+#3) -; CHECK-NEXT: r5 = memub(r1+#15) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r6 = asl(r6,#24) -; CHECK-NEXT: r5 = asl(r5,#24) -; CHECK-NEXT: r7 = memub(r1+#2) -; CHECK-NEXT: r9 = memub(r1+#14) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r6 |= asl(r7,#16) -; CHECK-NEXT: r5 |= asl(r9,#16) -; CHECK-NEXT: r14 = memub(r1+#1) -; CHECK-NEXT: r28 = memub(r1+#13) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r7 = asl(r14,#8) -; CHECK-NEXT: r8 = asl(r28,#8) -; CHECK-NEXT: r15 = memub(r1+#0) -; CHECK-NEXT: r11 = memub(r1+#12) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r6 |= or(r7,r15) -; CHECK-NEXT: r5 |= or(r8,r11) -; CHECK-NEXT: r7 = memub(r1+#7) -; CHECK-NEXT: r10 = memub(r1+#6) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r7 = asl(r7,#24) -; CHECK-NEXT: r12 = memub(r1+#5) -; CHECK-NEXT: memd(r29+#16) = r5:4 -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r7 |= asl(r10,#16) -; CHECK-NEXT: r12 = asl(r12,#8) -; CHECK-NEXT: r1 = memub(r1+#4) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r7 |= or(r12,r1) +; CHECK-NEXT: memd(r29+#8) = r5:4 +; CHECK-NEXT: memh(r29+#36) = ##18254 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: call printf -; CHECK-NEXT: memd(r29+#8) = r7:6 +; CHECK-NEXT: memw(r29+#32) = ##1230132307 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r0 = #0