From 44e4397abc827fab903992ad68ddca1964a81039 Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 20 Jul 2025 11:33:52 -0400 Subject: [PATCH 01/10] Pre-commit test (NFC) --- llvm/test/CodeGen/X86/cmp.ll | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index f3e141740b287..fb8a79571d98b 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -956,3 +956,16 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) { store i32 %z, ptr %y ret i1 %c } + +define i1 @sext_mask(i32 %a) { +; CHECK-LABEL: sext_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: movslq %edi, %rax # encoding: [0x48,0x63,0xc7] +; CHECK-NEXT: cmpq $-523, %rax # encoding: [0x48,0x3d,0xf5,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF5 +; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp slt i64 %a64, -523 + ret i1 %v1 +} From 33959557a88036df057fdd9648af5a860f415144 Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 20 Jul 2025 12:00:34 -0400 Subject: [PATCH 02/10] [X86] Try to shrink signed i64 compares if the input has enough one bits --- llvm/lib/Target/X86/X86ISelLowering.cpp | 16 +++++++++++++++- llvm/test/CodeGen/X86/cmp.ll | 3 +-- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d91ea1ea1bb1b..5d5d0c23376c7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23479,7 +23479,6 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, } // Try to shrink i64 compares if the input has enough zero bits. - // TODO: Add sign-bits equivalent for isX86CCSigned(X86CC)? if (CmpVT == MVT::i64 && !isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. DAG.MaskedValueIsZero(Op1, APInt::getHighBitsSet(64, 32)) && @@ -23489,6 +23488,21 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); } + // Try to shrink signed i64 compares if the input has enough one bits. + // Or the input is sign extended from a 32-bit value. + if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && + Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. + (DAG.MaskedValueIsAllOnes(Op1, APInt::getHighBitsSet(64, 32)) || + Op1.getOpcode() == ISD::SIGN_EXTEND || + Op1.getOpcode() == ISD::SIGN_EXTEND_INREG) && + (DAG.MaskedValueIsAllOnes(Op0, APInt::getHighBitsSet(64, 32)) || + Op0.getOpcode() == ISD::SIGN_EXTEND || + Op0.getOpcode() == ISD::SIGN_EXTEND_INREG)) { + CmpVT = MVT::i32; + Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0); + Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); + } + // 0-x == y --> x+y == 0 // 0-x != y --> x+y != 0 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op0.getOperand(0)) && diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index fb8a79571d98b..d71a7adafc652 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -960,8 +960,7 @@ define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) { define i1 @sext_mask(i32 %a) { ; CHECK-LABEL: sext_mask: ; CHECK: # %bb.0: -; CHECK-NEXT: movslq %edi, %rax # encoding: [0x48,0x63,0xc7] -; CHECK-NEXT: cmpq $-523, %rax # encoding: [0x48,0x3d,0xf5,0xfd,0xff,0xff] +; CHECK-NEXT: cmpl $-523, %edi # encoding: [0x81,0xff,0xf5,0xfd,0xff,0xff] ; CHECK-NEXT: # imm = 0xFDF5 ; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] From 77557197317ec2b64ae82562a95477d85410847b Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 20 Jul 2025 12:19:27 -0400 Subject: [PATCH 03/10] Comments --- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5d5d0c23376c7..909085a647be8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23490,6 +23490,8 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, // Try to shrink signed i64 compares if the input has enough one bits. // Or the input is sign extended from a 32-bit value. + // TODO: Should we peek through freeze? + // TODO: Is SIGN_EXTEND_INREG needed here? if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. (DAG.MaskedValueIsAllOnes(Op1, APInt::getHighBitsSet(64, 32)) || From 7eee49b1300ff455a83e0c18baf1eba4ac6a2fbd Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 20 Jul 2025 12:54:26 -0400 Subject: [PATCH 04/10] Use ComputeNumSignBits > 32 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 909085a647be8..5dea0c2536b56 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23494,10 +23494,10 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, // TODO: Is SIGN_EXTEND_INREG needed here? if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. - (DAG.MaskedValueIsAllOnes(Op1, APInt::getHighBitsSet(64, 32)) || + (DAG.ComputeNumSignBits(Op1) > 32 || Op1.getOpcode() == ISD::SIGN_EXTEND || Op1.getOpcode() == ISD::SIGN_EXTEND_INREG) && - (DAG.MaskedValueIsAllOnes(Op0, APInt::getHighBitsSet(64, 32)) || + (DAG.ComputeNumSignBits(Op0) > 32 || Op0.getOpcode() == ISD::SIGN_EXTEND || Op0.getOpcode() == ISD::SIGN_EXTEND_INREG)) { CmpVT = MVT::i32; From 0c2b42c000703d86e850dfc4b6d1789271f2c212 Mon Sep 17 00:00:00 2001 From: Rose Date: Wed, 23 Jul 2025 11:14:20 -0400 Subject: [PATCH 05/10] Address concerns --- llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +- llvm/test/CodeGen/X86/cmp.ll | 120 ++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5dea0c2536b56..5ab4b4d71b6e8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23490,16 +23490,9 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, // Try to shrink signed i64 compares if the input has enough one bits. // Or the input is sign extended from a 32-bit value. - // TODO: Should we peek through freeze? - // TODO: Is SIGN_EXTEND_INREG needed here? if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. - (DAG.ComputeNumSignBits(Op1) > 32 || - Op1.getOpcode() == ISD::SIGN_EXTEND || - Op1.getOpcode() == ISD::SIGN_EXTEND_INREG) && - (DAG.ComputeNumSignBits(Op0) > 32 || - Op0.getOpcode() == ISD::SIGN_EXTEND || - Op0.getOpcode() == ISD::SIGN_EXTEND_INREG)) { + DAG.ComputeNumSignBits(Op1) > 32 && DAG.ComputeNumSignBits(Op0) > 32) { CmpVT = MVT::i32; Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0); Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index d71a7adafc652..6acb75d2c9594 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -968,3 +968,123 @@ define i1 @sext_mask(i32 %a) { %v1 = icmp slt i64 %a64, -523 ret i1 %v1 } + +define i1 @sext_i9_mask(i9 %a) { +; NO-NDD-LABEL: sext_i9_mask: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NO-NDD-NEXT: shlq $55, %rdi # encoding: [0x48,0xc1,0xe7,0x37] +; NO-NDD-NEXT: sarq $55, %rdi # encoding: [0x48,0xc1,0xff,0x37] +; NO-NDD-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF6 +; NO-NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: sext_i9_mask: +; NDD: # %bb.0: +; NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NDD-NEXT: shlq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x37] +; NDD-NEXT: sarq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x37] +; NDD-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF6 +; NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i9 %a to i64 + %v1 = icmp slt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @sext_i32_mask(i32 %a) { +; CHECK-LABEL: sext_i32_mask: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpl $-522, %edi # encoding: [0x81,0xff,0xf6,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF6 +; CHECK-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp slt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @i40(i40 %a) { +; NO-NDD-LABEL: i40: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setl %al # encoding: [0x0f,0x9c,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp slt i64 %a64, -521 + ret i1 %v1 +} + +define i1 @sext_i9_mask_sgt(i9 %a) { +; NO-NDD-LABEL: sext_i9_mask_sgt: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NO-NDD-NEXT: shlq $55, %rdi # encoding: [0x48,0xc1,0xe7,0x37] +; NO-NDD-NEXT: sarq $55, %rdi # encoding: [0x48,0xc1,0xff,0x37] +; NO-NDD-NEXT: cmpl $-520, %edi # encoding: [0x81,0xff,0xf8,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF8 +; NO-NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: sext_i9_mask_sgt: +; NDD: # %bb.0: +; NDD-NEXT: # kill: def $edi killed $edi def $rdi +; NDD-NEXT: shlq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x37] +; NDD-NEXT: sarq $55, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x37] +; NDD-NEXT: cmpl $-520, %edi # encoding: [0x81,0xff,0xf8,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF8 +; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i9 %a to i64 + %v1 = icmp sgt i64 %a64, -521 + ret i1 %v1 +} + +define i1 @sext_i32_mask_sgt(i32 %a) { +; CHECK-LABEL: sext_i32_mask_sgt: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpl $-521, %edi # encoding: [0x81,0xff,0xf7,0xfd,0xff,0xff] +; CHECK-NEXT: # imm = 0xFDF7 +; CHECK-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; CHECK-NEXT: retq # encoding: [0xc3] + %a64 = sext i32 %a to i64 + %v1 = icmp sgt i64 %a64, -522 + ret i1 %v1 +} + +define i1 @i40_sge(i40 %a) { +; NO-NDD-LABEL: i40_sge: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_sge: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp sge i64 %a64, -521 + ret i1 %v1 +} From bdc83c2997b267e3c9e0d508db9456427ad75f52 Mon Sep 17 00:00:00 2001 From: Rose Date: Wed, 23 Jul 2025 14:56:40 -0400 Subject: [PATCH 06/10] Improve comment --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5ab4b4d71b6e8..44a622102bb63 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23488,8 +23488,8 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); } - // Try to shrink signed i64 compares if the input has enough one bits. - // Or the input is sign extended from a 32-bit value. + // Try to shrink signed i64 compares if the inputs are representable as signed + // i32. if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. DAG.ComputeNumSignBits(Op1) > 32 && DAG.ComputeNumSignBits(Op0) > 32) { From 67f9a5c048da2ab756f588eb5ea280d50c41db2d Mon Sep 17 00:00:00 2001 From: Rose Date: Sat, 26 Jul 2025 17:28:29 -0400 Subject: [PATCH 07/10] Add isX86CCUnsigned So that equality comparisons also work. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 44a622102bb63..ffcdd3a636172 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2959,6 +2959,26 @@ static bool isX86CCSigned(X86::CondCode X86CC) { } } +/// Return true if the condition is an unsigned comparison operation. +static bool isX86CCUnsigned(X86::CondCode X86CC) { + switch (X86CC) { + case X86::COND_B: + case X86::COND_A: + case X86::COND_BE: + case X86::COND_AE: + return true; + case X86::COND_E: + case X86::COND_NE: + case X86::COND_G: + case X86::COND_GE: + case X86::COND_L: + case X86::COND_LE: + default: + llvm_unreachable("Invalid integer condition!"); + return false; + } +} + static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) { switch (SetCCOpcode) { // clang-format off @@ -23490,7 +23510,7 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, // Try to shrink signed i64 compares if the inputs are representable as signed // i32. - if (CmpVT == MVT::i64 && isX86CCSigned(X86CC) && + if (CmpVT == MVT::i64 && !isX86CCUnsigned(X86CC) && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. DAG.ComputeNumSignBits(Op1) > 32 && DAG.ComputeNumSignBits(Op0) > 32) { CmpVT = MVT::i32; From c8bb79aaa6209fb136140689a79466ffbb6769d7 Mon Sep 17 00:00:00 2001 From: Rose Date: Sat, 26 Jul 2025 20:04:40 -0400 Subject: [PATCH 08/10] Fix error --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ffcdd3a636172..14ca6c7b47ba2 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2967,14 +2967,14 @@ static bool isX86CCUnsigned(X86::CondCode X86CC) { case X86::COND_BE: case X86::COND_AE: return true; + default: + llvm_unreachable("Invalid integer condition!"); case X86::COND_E: case X86::COND_NE: case X86::COND_G: case X86::COND_GE: case X86::COND_L: case X86::COND_LE: - default: - llvm_unreachable("Invalid integer condition!"); return false; } } From 28cef73aa0af27f0ff44f83459abe27f35c97088 Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 27 Jul 2025 11:13:34 -0400 Subject: [PATCH 09/10] Remove unsigned check --- llvm/lib/Target/X86/X86ISelLowering.cpp | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 14ca6c7b47ba2..5cec752d1457a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2959,26 +2959,6 @@ static bool isX86CCSigned(X86::CondCode X86CC) { } } -/// Return true if the condition is an unsigned comparison operation. -static bool isX86CCUnsigned(X86::CondCode X86CC) { - switch (X86CC) { - case X86::COND_B: - case X86::COND_A: - case X86::COND_BE: - case X86::COND_AE: - return true; - default: - llvm_unreachable("Invalid integer condition!"); - case X86::COND_E: - case X86::COND_NE: - case X86::COND_G: - case X86::COND_GE: - case X86::COND_L: - case X86::COND_LE: - return false; - } -} - static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) { switch (SetCCOpcode) { // clang-format off @@ -23508,9 +23488,9 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, X86::CondCode X86CC, Op1 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op1); } - // Try to shrink signed i64 compares if the inputs are representable as signed + // Try to shrink all i64 compares if the inputs are representable as signed // i32. - if (CmpVT == MVT::i64 && !isX86CCUnsigned(X86CC) && + if (CmpVT == MVT::i64 && Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub. DAG.ComputeNumSignBits(Op1) > 32 && DAG.ComputeNumSignBits(Op0) > 32) { CmpVT = MVT::i32; From 5631b139611da0657638ddaf073901056cb718a9 Mon Sep 17 00:00:00 2001 From: Rose Date: Sun, 27 Jul 2025 11:57:30 -0400 Subject: [PATCH 10/10] Add new tests for eq and unsigned checks --- llvm/test/CodeGen/X86/cmp.ll | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index 6acb75d2c9594..ed3f0e0f0aa71 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -1088,3 +1088,53 @@ define i1 @i40_sge(i40 %a) { %v1 = icmp sge i64 %a64, -521 ret i1 %v1 } + +define i1 @i40_eq(i40 %a) { +; NO-NDD-LABEL: i40_eq: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movabsq $1099511627775, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFFFFFF +; NO-NDD-NEXT: andq %rdi, %rax # encoding: [0x48,0x21,0xf8] +; NO-NDD-NEXT: movabsq $1099511627255, %rcx # encoding: [0x48,0xb9,0xf7,0xfd,0xff,0xff,0xff,0x00,0x00,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFFFDF7 +; NO-NDD-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_eq: +; NDD: # %bb.0: +; NDD-NEXT: movabsq $1099511627775, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00] +; NDD-NEXT: # imm = 0xFFFFFFFFFF +; NDD-NEXT: andq %rdi, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xf8] +; NDD-NEXT: movabsq $1099511627255, %rcx # encoding: [0x48,0xb9,0xf7,0xfd,0xff,0xff,0xff,0x00,0x00,0x00] +; NDD-NEXT: # imm = 0xFFFFFFFDF7 +; NDD-NEXT: cmpq %rcx, %rax # encoding: [0x48,0x39,0xc8] +; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp eq i64 %a64, -521 + ret i1 %v1 +} + +define i1 @i40_ult(i40 %a) { +; NO-NDD-LABEL: i40_ult: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shlq $24, %rdi # encoding: [0x48,0xc1,0xe7,0x18] +; NO-NDD-NEXT: sarq $24, %rdi # encoding: [0x48,0xc1,0xff,0x18] +; NO-NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NO-NDD-NEXT: # imm = 0xFDF7 +; NO-NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] +; +; NDD-LABEL: i40_ult: +; NDD: # %bb.0: +; NDD-NEXT: shlq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xe7,0x18] +; NDD-NEXT: sarq $24, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0xc1,0xff,0x18] +; NDD-NEXT: cmpq $-521, %rdi # encoding: [0x48,0x81,0xff,0xf7,0xfd,0xff,0xff] +; NDD-NEXT: # imm = 0xFDF7 +; NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] +; NDD-NEXT: retq # encoding: [0xc3] + %a64 = sext i40 %a to i64 + %v1 = icmp ult i64 %a64, -521 + ret i1 %v1 +}