From d5363696bf6a14758de7e3040d92448fc7e054f4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 28 Jul 2025 11:41:33 -0700 Subject: [PATCH] [RISCV] Add IsSignExtendingOpW to P-ext CLS, CLSW, and ABSW instructions. This matches other W instructions. CLS is included since it can only return 0-63 which has bits [63:31] as zero. This is similar to CLZ. This doesn't do anything yet since we don't have CodeGen support for P. --- llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index dd365cfa1379b..8297d5050ceda 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -136,6 +136,7 @@ class RVPUnary_ri w, bits<5> uf, string opcodestr> //===----------------------------------------------------------------------===// let Predicates = [HasStdExtP] in { +let IsSignExtendingOpW = 1 in def CLS : Unary_r<0b011000000011, 0b001, "cls">; def ABS : Unary_r<0b011000000111, 0b001, "abs">; } // Predicates = [HasStdExtP] @@ -146,8 +147,10 @@ let Predicates = [HasStdExtP, IsRV64] in { def REV16 : Unary_r<0b011010110000, 0b101, "rev16">; def REV_RV64 : Unary_r<0b011010111111, 0b101, "rev">; +let IsSignExtendingOpW = 1 in { def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">; def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">; +} } // Predicates = [HasStdExtP, IsRV64] let Predicates = [HasStdExtP] in {