From 7078f7d68512b32c2375b29ad7b23d87520f870b Mon Sep 17 00:00:00 2001 From: Alexandre Eichenberger Date: Tue, 29 Jul 2025 20:12:51 -0400 Subject: [PATCH 1/3] add MemWrite side effect to memref.prefetch Signed-off-by: Alexandre Eichenberger --- mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td | 3 ++- .../OwnershipBasedBufferDeallocation/misc-other.mlir | 10 +++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td index 9321089ab55fa..3a249410cfa88 100644 --- a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td +++ b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td @@ -1351,7 +1351,8 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> { instruction cache. }]; - let arguments = (ins AnyMemRef:$memref, Variadic:$indices, + let arguments = (ins Arg :$memref, + Variadic:$indices, BoolAttr:$isWrite, ConfinedAttr, IntMaxValue<3>]>:$localityHint, diff --git a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir index c50c25ad8194f..2ff3587e8998f 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir @@ -17,4 +17,12 @@ func.func @func_with_assert(%arg0: index, %arg1: index) { func.func @func_with_assume_alignment(%arg0: memref<128xi8>) { %0 = memref.assume_alignment %arg0, 64 : memref<128xi8> return -} \ No newline at end of file +} + +// CHECK-LABEL: func @func_with_prefetch( +// CHECK: memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32> +func.func @func_with_prefetch(%arg0: memref<4x8xf32>) { + %c0 = arith.constant 0 : index + memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32> + return +} From 3a7212a5b2989f13897e3f3eff0056115352887a Mon Sep 17 00:00:00 2001 From: Alexandre Eichenberger Date: Tue, 29 Jul 2025 20:18:53 -0400 Subject: [PATCH 2/3] added memref.prefetch MemWrite side effect Signed-off-by: Alexandre Eichenberger --- mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td | 2 +- .../Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td index 3a249410cfa88..5a46e86eca2b5 100644 --- a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td +++ b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td @@ -1351,7 +1351,7 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> { instruction cache. }]; - let arguments = (ins Arg :$memref, + let arguments = (ins Arg :$memref, Variadic:$indices, BoolAttr:$isWrite, ConfinedAttr, diff --git a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir index 2ff3587e8998f..fc137f1f2f722 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir @@ -24,5 +24,5 @@ func.func @func_with_assume_alignment(%arg0: memref<128xi8>) { func.func @func_with_prefetch(%arg0: memref<4x8xf32>) { %c0 = arith.constant 0 : index memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32> - return + return } From 429910e0a578ff0b510926f1397eecf6200c75dc Mon Sep 17 00:00:00 2001 From: Alexandre Eichenberger Date: Fri, 1 Aug 2025 10:20:04 -0400 Subject: [PATCH 3/3] added comments to responde to review Signed-off-by: Alexandre Eichenberger --- mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td | 3 +++ 1 file changed, 3 insertions(+) diff --git a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td index 5a46e86eca2b5..79ed47dd9e765 100644 --- a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td +++ b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td @@ -1351,6 +1351,9 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> { instruction cache. }]; + // The memref argument is labeled with a MemWrite side effect to enforce a + // relative ordering of the prefetch and other memory operations targeting + // that memory stream. let arguments = (ins Arg :$memref, Variadic:$indices, BoolAttr:$isWrite,