From 770bd40386171386cf0055715b7681522b644141 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0@owo.li>
Date: Mon, 4 Aug 2025 22:46:46 +0800
Subject: [PATCH 1/3] [RISCV] Create disjoint or in RISCVGatherScatterLowering

---
 llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
index 82c0d8d4738a4..28567ada6c004 100644
--- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -167,9 +167,8 @@ static std::pair<Value *, Value *> matchStridedStart(Value *Start,
   default:
     llvm_unreachable("Unexpected opcode");
   case Instruction::Or:
-    // TODO: We'd be better off creating disjoint or here, but we don't yet
-    // have an IRBuilder API for that.
-    [[fallthrough]];
+    Start = Builder.CreateOr(Start, Splat, "", /* IsDisjoint = */ true);
+    break;
   case Instruction::Add:
     Start = Builder.CreateAdd(Start, Splat);
     break;

From 62c43b0178f315e3c98df462d63a2c372a291bfe Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0@owo.li>
Date: Tue, 5 Aug 2025 11:38:51 +0800
Subject: [PATCH 2/3] update test

---
 llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
index 7039bf49be465..09f42eed026c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll
@@ -467,7 +467,7 @@ define <vscale x 1 x i64> @straightline_offset_disjoint_or_1(ptr %p) {
 define <vscale x 1 x i64> @straightline_offset_disjoint_or(ptr %p, i1 %offset) {
 ; CHECK-LABEL: @straightline_offset_disjoint_or(
 ; CHECK-NEXT:    [[AND:%.*]] = zext i1 [[OFFSET:%.*]] to i64
-; CHECK-NEXT:    [[TMP4:%.*]] = add i64 4, [[AND]]
+; CHECK-NEXT:    [[TMP4:%.*]] = or disjoint i64 4, [[AND]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP4]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @llvm.vscale.i32()
 ; CHECK-NEXT:    [[TMP3:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i64(ptr [[TMP1]], i64 8, <vscale x 1 x i1> splat (i1 true), i32 [[TMP2]])

From 6492cb411a7a885f75dce49e3d3fd4b23cf55701 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0@owo.li>
Date: Tue, 5 Aug 2025 11:39:32 +0800
Subject: [PATCH 3/3] Update
 llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp

Co-authored-by: Min-Yih Hsu <min.hsu@sifive.com>
---
 llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
index 28567ada6c004..80a48c5ec11fc 100644
--- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -167,7 +167,7 @@ static std::pair<Value *, Value *> matchStridedStart(Value *Start,
   default:
     llvm_unreachable("Unexpected opcode");
   case Instruction::Or:
-    Start = Builder.CreateOr(Start, Splat, "", /* IsDisjoint = */ true);
+    Start = Builder.CreateOr(Start, Splat, "", /*IsDisjoint=*/true);
     break;
   case Instruction::Add:
     Start = Builder.CreateAdd(Start, Splat);