diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
index dc4f811e075c6..2af3e8f0eac80 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -46,23 +46,11 @@ enum CondCodes { // Meaning (integer)          Meaning (floating-point)
 };
 
 inline static CondCodes getOppositeCondition(CondCodes CC) {
-  switch (CC) {
-  default: llvm_unreachable("Unknown condition code");
-  case EQ: return NE;
-  case NE: return EQ;
-  case HS: return LO;
-  case LO: return HS;
-  case MI: return PL;
-  case PL: return MI;
-  case VS: return VC;
-  case VC: return VS;
-  case HI: return LS;
-  case LS: return HI;
-  case GE: return LT;
-  case LT: return GE;
-  case GT: return LE;
-  case LE: return GT;
-  }
+  // To reverse a condition it's necessary to only invert the low bit:
+  // Note that unlike in AArch64, flipping the bottom bit for AL is not a valid
+  // predicate.
+  assert(CC != AL && "AL has no opposite condition");
+  return static_cast<CondCodes>(static_cast<unsigned>(CC) ^ 0x1);
 }
 
 /// getSwappedCondition - assume the flags are set by MI(a,b), return
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 085064eee896a..616895705058e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1129,22 +1129,9 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
 }
 
 RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Unrecognized conditional branch");
-  case RISCVCC::COND_EQ:
-    return RISCVCC::COND_NE;
-  case RISCVCC::COND_NE:
-    return RISCVCC::COND_EQ;
-  case RISCVCC::COND_LT:
-    return RISCVCC::COND_GE;
-  case RISCVCC::COND_GE:
-    return RISCVCC::COND_LT;
-  case RISCVCC::COND_LTU:
-    return RISCVCC::COND_GEU;
-  case RISCVCC::COND_GEU:
-    return RISCVCC::COND_LTU;
-  }
+  // To reverse a condition it's necessary to only invert the low bit:
+  assert(CC != RISCVCC::COND_INVALID && "COND_INVALID has no inverse!");
+  return static_cast<RISCVCC::CondCode>(static_cast<unsigned>(CC) ^ 0x1);
 }
 
 bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index abf365eedec39..8841e866b0bb4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3300,46 +3300,9 @@ unsigned X86::getNonNDVariant(unsigned Opc) {
 /// Return the inverse of the specified condition,
 /// e.g. turning COND_E to COND_NE.
 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
-  switch (CC) {
-  default:
-    llvm_unreachable("Illegal condition code!");
-  case X86::COND_E:
-    return X86::COND_NE;
-  case X86::COND_NE:
-    return X86::COND_E;
-  case X86::COND_L:
-    return X86::COND_GE;
-  case X86::COND_LE:
-    return X86::COND_G;
-  case X86::COND_G:
-    return X86::COND_LE;
-  case X86::COND_GE:
-    return X86::COND_L;
-  case X86::COND_B:
-    return X86::COND_AE;
-  case X86::COND_BE:
-    return X86::COND_A;
-  case X86::COND_A:
-    return X86::COND_BE;
-  case X86::COND_AE:
-    return X86::COND_B;
-  case X86::COND_S:
-    return X86::COND_NS;
-  case X86::COND_NS:
-    return X86::COND_S;
-  case X86::COND_P:
-    return X86::COND_NP;
-  case X86::COND_NP:
-    return X86::COND_P;
-  case X86::COND_O:
-    return X86::COND_NO;
-  case X86::COND_NO:
-    return X86::COND_O;
-  case X86::COND_NE_OR_P:
-    return X86::COND_E_AND_NP;
-  case X86::COND_E_AND_NP:
-    return X86::COND_NE_OR_P;
-  }
+  // To reverse a condition it's necessary to only invert the low bit:
+  assert(CC != COND_INVALID && "COND_INVALID has no inverse!");
+  return static_cast<CondCode>(static_cast<unsigned>(CC) ^ 0x1);
 }
 
 /// Assuming the flags are set by MI(a,b), return the condition code if we