@@ -91,16 +91,16 @@ pub enum Mid<T> {
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pub fn mid_bool_eq_discr ( a : Mid < bool > , b : Mid < bool > ) -> bool {
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// CHECK-LABEL: @mid_bool_eq_discr(
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+ // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %a, 3
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+ // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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// CHECK: %[[A_REL_DISCR:.+]] = add nsw i8 %a, -2
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// CHECK: %[[A_IS_NICHE:.+]] = icmp samesign ugt i8 %a, 1
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- // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %[[A_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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// CHECK: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %[[A_REL_DISCR]], i8 1
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+ // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %b, 3
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+ // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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// CHECK: %[[B_REL_DISCR:.+]] = add nsw i8 %b, -2
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// CHECK: %[[B_IS_NICHE:.+]] = icmp samesign ugt i8 %b, 1
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- // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %[[B_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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// CHECK: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %[[B_REL_DISCR]], i8 1
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// CHECK: ret i1 %[[R]]
@@ -111,16 +111,16 @@ pub fn mid_bool_eq_discr(a: Mid<bool>, b: Mid<bool>) -> bool {
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pub fn mid_ord_eq_discr ( a : Mid < Ordering > , b : Mid < Ordering > ) -> bool {
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// CHECK-LABEL: @mid_ord_eq_discr(
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+ // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %a, 3
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+ // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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// CHECK: %[[A_REL_DISCR:.+]] = add nsw i8 %a, -2
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// CHECK: %[[A_IS_NICHE:.+]] = icmp sgt i8 %a, 1
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- // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %[[A_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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// CHECK: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %[[A_REL_DISCR]], i8 1
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+ // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %b, 3
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+ // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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// CHECK: %[[B_REL_DISCR:.+]] = add nsw i8 %b, -2
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// CHECK: %[[B_IS_NICHE:.+]] = icmp sgt i8 %b, 1
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- // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %[[B_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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// CHECK: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %[[B_REL_DISCR]], i8 1
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// CHECK: %[[R:.+]] = icmp eq i8 %[[A_DISCR]], %[[B_DISCR]]
@@ -140,16 +140,16 @@ pub fn mid_nz32_eq_discr(a: Mid<NonZero<u32>>, b: Mid<NonZero<u32>>) -> bool {
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pub fn mid_ac_eq_discr ( a : Mid < AC > , b : Mid < AC > ) -> bool {
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// CHECK-LABEL: @mid_ac_eq_discr(
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- // LLVM20: %[[A_REL_DISCR:.+]] = xor i8 %a, -128
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- // CHECK: %[[A_IS_NICHE:.+]] = icmp slt i8 %a, 0
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// CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i8 %a, -127
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// CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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+ // LLVM20: %[[A_REL_DISCR:.+]] = xor i8 %a, -128
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+ // CHECK: %[[A_IS_NICHE:.+]] = icmp slt i8 %a, 0
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// LLVM20: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %[[A_REL_DISCR]], i8 1
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- // LLVM20: %[[B_REL_DISCR:.+]] = xor i8 %b, -128
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- // CHECK: %[[B_IS_NICHE:.+]] = icmp slt i8 %b, 0
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// CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i8 %b, -127
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// CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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+ // LLVM20: %[[B_REL_DISCR:.+]] = xor i8 %b, -128
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+ // CHECK: %[[B_IS_NICHE:.+]] = icmp slt i8 %b, 0
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// LLVM20: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i8 %[[B_REL_DISCR]], i8 1
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// LLVM21: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i8 %a, i8 -127
@@ -166,21 +166,24 @@ pub fn mid_ac_eq_discr(a: Mid<AC>, b: Mid<AC>) -> bool {
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pub fn mid_giant_eq_discr ( a : Mid < Giant > , b : Mid < Giant > ) -> bool {
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// CHECK-LABEL: @mid_giant_eq_discr(
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+ // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i128 %a, 6
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+ // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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// CHECK: %[[A_TRUNC:.+]] = trunc nuw nsw i128 %a to i64
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- // CHECK : %[[A_REL_DISCR:.+]] = add nsw i64 %[[A_TRUNC]], -5
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+ // LLVM20 : %[[A_REL_DISCR:.+]] = add nsw i64 %[[A_TRUNC]], -5
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// CHECK: %[[A_IS_NICHE:.+]] = icmp samesign ugt i128 %a, 4
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- // CHECK: %[[A_NOT_HOLE:.+]] = icmp ne i64 %[[A_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[A_NOT_HOLE]])
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- // CHECK: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i64 %[[A_REL_DISCR]], i64 1
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+ // LLVM20: %[[A_DISCR:.+]] = select i1 %[[A_IS_NICHE]], i64 %[[A_REL_DISCR]], i64 1
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+ // LLVM21: %[[A_MODIFIED_TAG:.+]] = select i1 %[[A_IS_NICHE]], i64 %[[A_TRUNC]], i64 6
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+ // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i128 %b, 6
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+ // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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// CHECK: %[[B_TRUNC:.+]] = trunc nuw nsw i128 %b to i64
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- // CHECK : %[[B_REL_DISCR:.+]] = add nsw i64 %[[B_TRUNC]], -5
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+ // LLVM20 : %[[B_REL_DISCR:.+]] = add nsw i64 %[[B_TRUNC]], -5
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// CHECK: %[[B_IS_NICHE:.+]] = icmp samesign ugt i128 %b, 4
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- // CHECK: %[[B_NOT_HOLE:.+]] = icmp ne i64 %[[B_REL_DISCR]], 1
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- // CHECK: tail call void @llvm.assume(i1 %[[B_NOT_HOLE]])
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- // CHECK: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i64 %[[B_REL_DISCR]], i64 1
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+ // LLVM20: %[[B_DISCR:.+]] = select i1 %[[B_IS_NICHE]], i64 %[[B_REL_DISCR]], i64 1
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+ // LLVM21: %[[B_MODIFIED_TAG:.+]] = select i1 %[[B_IS_NICHE]], i64 %[[B_TRUNC]], i64 6
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- // CHECK: %[[R:.+]] = icmp eq i64 %[[A_DISCR]], %[[B_DISCR]]
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+ // LLVM20: %[[R:.+]] = icmp eq i64 %[[A_DISCR]], %[[B_DISCR]]
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+ // LLVM21: %[[R:.+]] = icmp eq i64 %[[A_MODIFIED_TAG]], %[[B_MODIFIED_TAG]]
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// CHECK: ret i1 %[[R]]
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discriminant_value ( & a) == discriminant_value ( & b)
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}
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