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Revert part of "Fix tests."
This reverts commit 9f47e26.
1 parent 8f73dfa commit b74d2a3

20 files changed

+1553
-1546
lines changed

tests/assembly-llvm/asm/aarch64-modifiers.rs

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -55,17 +55,35 @@ check!(vreg vreg "add {0}.4s, {0}.4s, {0}.4s");
5555
// CHECK: //NO_APP
5656
check!(vreg_b vreg "ldr {:b}, [x0]");
5757

58+
// CHECK-LABEL: vreg_h:
59+
// CHECK: //APP
60+
// CHECK: ldr h0, [x0]
61+
// CHECK: //NO_APP
62+
check!(vreg_h vreg "ldr {:h}, [x0]");
63+
64+
// CHECK-LABEL: vreg_s:
65+
// CHECK: //APP
66+
// CHECK: ldr s0, [x0]
67+
// CHECK: //NO_APP
68+
check!(vreg_s vreg "ldr {:s}, [x0]");
69+
5870
// CHECK-LABEL: vreg_d:
5971
// CHECK: //APP
6072
// CHECK: ldr d0, [x0]
6173
// CHECK: //NO_APP
6274
check!(vreg_d vreg "ldr {:d}, [x0]");
6375

64-
// CHECK-LABEL: vreg_h:
76+
// CHECK-LABEL: vreg_q:
6577
// CHECK: //APP
66-
// CHECK: ldr h0, [x0]
78+
// CHECK: ldr q0, [x0]
6779
// CHECK: //NO_APP
68-
check!(vreg_h vreg "ldr {:h}, [x0]");
80+
check!(vreg_q vreg "ldr {:q}, [x0]");
81+
82+
// CHECK-LABEL: vreg_v:
83+
// CHECK: //APP
84+
// CHECK: add v0.4s, v0.4s, v0.4s
85+
// CHECK: //NO_APP
86+
check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
6987

7088
// CHECK-LABEL: vreg_low16:
7189
// CHECK: //APP
@@ -79,50 +97,32 @@ check!(vreg_low16 vreg_low16 "add {0}.4s, {0}.4s, {0}.4s");
7997
// CHECK: //NO_APP
8098
check!(vreg_low16_b vreg_low16 "ldr {:b}, [x0]");
8199

82-
// CHECK-LABEL: vreg_low16_d:
83-
// CHECK: //APP
84-
// CHECK: ldr d0, [x0]
85-
// CHECK: //NO_APP
86-
check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
87-
88100
// CHECK-LABEL: vreg_low16_h:
89101
// CHECK: //APP
90102
// CHECK: ldr h0, [x0]
91103
// CHECK: //NO_APP
92104
check!(vreg_low16_h vreg_low16 "ldr {:h}, [x0]");
93105

94-
// CHECK-LABEL: vreg_low16_q:
95-
// CHECK: //APP
96-
// CHECK: ldr q0, [x0]
97-
// CHECK: //NO_APP
98-
check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
99-
100106
// CHECK-LABEL: vreg_low16_s:
101107
// CHECK: //APP
102108
// CHECK: ldr s0, [x0]
103109
// CHECK: //NO_APP
104110
check!(vreg_low16_s vreg_low16 "ldr {:s}, [x0]");
105111

106-
// CHECK-LABEL: vreg_low16_v:
112+
// CHECK-LABEL: vreg_low16_d:
107113
// CHECK: //APP
108-
// CHECK: add v0.4s, v0.4s, v0.4s
114+
// CHECK: ldr d0, [x0]
109115
// CHECK: //NO_APP
110-
check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
116+
check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
111117

112-
// CHECK-LABEL: vreg_q:
118+
// CHECK-LABEL: vreg_low16_q:
113119
// CHECK: //APP
114120
// CHECK: ldr q0, [x0]
115121
// CHECK: //NO_APP
116-
check!(vreg_q vreg "ldr {:q}, [x0]");
117-
118-
// CHECK-LABEL: vreg_s:
119-
// CHECK: //APP
120-
// CHECK: ldr s0, [x0]
121-
// CHECK: //NO_APP
122-
check!(vreg_s vreg "ldr {:s}, [x0]");
122+
check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
123123

124-
// CHECK-LABEL: vreg_v:
124+
// CHECK-LABEL: vreg_low16_v:
125125
// CHECK: //APP
126126
// CHECK: add v0.4s, v0.4s, v0.4s
127127
// CHECK: //NO_APP
128-
check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
128+
check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");

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