From 2e49c52855c6a726d4f42705fe42d3c237f14b32 Mon Sep 17 00:00:00 2001 From: Caiweiran Date: Wed, 23 Jul 2025 11:23:36 +0000 Subject: [PATCH] Fix tests/codegen-llvm/const-vector.rs test failure on riscv64 --- tests/codegen-llvm/const-vector.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/codegen-llvm/const-vector.rs b/tests/codegen-llvm/const-vector.rs index a2249f4fff7bf..f430749234111 100644 --- a/tests/codegen-llvm/const-vector.rs +++ b/tests/codegen-llvm/const-vector.rs @@ -15,6 +15,7 @@ #![feature(arm_target_feature)] #![feature(mips_target_feature)] #![allow(non_camel_case_types)] +#![feature(riscv_target_feature)] #[path = "../auxiliary/minisimd.rs"] mod minisimd; @@ -42,6 +43,7 @@ extern "unadjusted" { #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub fn do_call() { unsafe { // CHECK: call void @test_i8x2(<2 x i8>