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[PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC]
1 parent 5d67fb3 commit 06c810b

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2 files changed

+135
-132
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2 files changed

+135
-132
lines changed

‎llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

Lines changed: 65 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,18 @@
1-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
1+
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
2+
; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
23
; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
34

45
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
56
; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \
6-
; RUN: FileCheck --check-prefixes=CHECKASM,ASM32PWR4 %s
7+
; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s
78

8-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
9+
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
10+
; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
911
; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
1012

1113
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
1214
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
13-
; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
15+
; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s
1416

1517
%struct.S1 = type { [1 x i8] }
1618
@gS1 = external global %struct.S1, align 1
@@ -34,13 +36,13 @@ declare void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1)
3436

3537
; CHECKASM-LABEL: .call_test_byval_1Byte:
3638

37-
; ASM32PWR4: stwu 1, -64(1)
38-
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
39-
; ASM32PWR4-NEXT: lbz 3, 0([[REG]])
40-
; ASM32PWR4-NEXT: slwi 3, 3, 24
41-
; ASM32PWR4-NEXT: bl .test_byval_1Byte
42-
; ASM32PWR4-NEXT: nop
43-
; ASM32PWR4-NEXT: addi 1, 1, 64
39+
; ASM32: stwu 1, -64(1)
40+
; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
41+
; ASM32-NEXT: lbz 3, 0([[REG]])
42+
; ASM32-NEXT: slwi 3, 3, 24
43+
; ASM32-NEXT: bl .test_byval_1Byte
44+
; ASM32-NEXT: nop
45+
; ASM32-NEXT: addi 1, 1, 64
4446

4547
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
4648
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
@@ -49,14 +51,14 @@ declare void @test_byval_1Byte(%struct.S1* byval(%struct.S1) align 1)
4951
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
5052
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
5153

52-
; ASM64PWR4: std 0, 16(1)
53-
; ASM64PWR4-NEXT: stdu 1, -112(1)
54-
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
55-
; ASM64PWR4-NEXT: lbz 3, 0([[REG]])
56-
; ASM64PWR4-NEXT: sldi 3, 3, 56
57-
; ASM64PWR4-NEXT: bl .test_byval_1Byte
58-
; ASM64PWR4-NEXT: nop
59-
; ASM64PWR4-NEXT: addi 1, 1, 112
54+
; ASM64: std 0, 16(1)
55+
; ASM64-NEXT: stdu 1, -112(1)
56+
; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
57+
; ASM64-NEXT: lbz 3, 0([[REG]])
58+
; ASM64-NEXT: sldi 3, 3, 56
59+
; ASM64-NEXT: bl .test_byval_1Byte
60+
; ASM64-NEXT: nop
61+
; ASM64-NEXT: addi 1, 1, 112
6062

6163
%struct.S2 = type { [2 x i8] }
6264

@@ -81,13 +83,13 @@ declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
8183

8284
; CHECKASM-LABEL: .call_test_byval_2Byte:
8385

84-
; ASM32PWR4: stwu 1, -64(1)
85-
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
86-
; ASM32PWR4-NEXT: lhz 3, 0([[REG]])
87-
; ASM32PWR4-NEXT: slwi 3, 3, 16
88-
; ASM32PWR4-NEXT: bl .test_byval_2Byte
89-
; ASM32PWR4-NEXT: nop
90-
; ASM32PWR4-NEXT: addi 1, 1, 64
86+
; ASM32: stwu 1, -64(1)
87+
; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
88+
; ASM32-NEXT: lhz 3, 0([[REG]])
89+
; ASM32-NEXT: slwi 3, 3, 16
90+
; ASM32-NEXT: bl .test_byval_2Byte
91+
; ASM32-NEXT: nop
92+
; ASM32-NEXT: addi 1, 1, 64
9193

9294
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
9395
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS2, $x2 :: (load 8 from got)
@@ -96,14 +98,14 @@ declare void @test_byval_2Byte(%struct.S2* byval(%struct.S2) align 1)
9698
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
9799
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
98100

99-
; ASM64PWR4: std 0, 16(1)
100-
; ASM64PWR4-NEXT: stdu 1, -112(1)
101-
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
102-
; ASM64PWR4-NEXT: lhz 3, 0([[REG]])
103-
; ASM64PWR4-NEXT: sldi 3, 3, 48
104-
; ASM64PWR4-NEXT: bl .test_byval_2Byte
105-
; ASM64PWR4-NEXT: nop
106-
; ASM64PWR4-NEXT: addi 1, 1, 112
101+
; ASM64: std 0, 16(1)
102+
; ASM64-NEXT: stdu 1, -112(1)
103+
; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
104+
; ASM64-NEXT: lhz 3, 0([[REG]])
105+
; ASM64-NEXT: sldi 3, 3, 48
106+
; ASM64-NEXT: bl .test_byval_2Byte
107+
; ASM64-NEXT: nop
108+
; ASM64-NEXT: addi 1, 1, 112
107109

108110
%struct.S3 = type { [3 x i8] }
109111

@@ -132,14 +134,14 @@ declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
132134
; CHECKASM-LABEL: .call_test_byval_3Byte:
133135

134136
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
135-
; ASM32PWR4: stwu 1, -64(1)
136-
; ASM32PWR4-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
137-
; ASM32PWR4-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
138-
; ASM32PWR4-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
139-
; ASM32PWR4-DAG: rlwinm 3, [[REG2]], 8, 16, 23
140-
; ASM32PWR4-DAG: rlwimi 3, [[REG1]], 16, 0, 15
141-
; ASM32PWR4-NEXT: bl .test_byval_3Byte
142-
; ASM32PWR4-NEXT: nop
137+
; ASM32: stwu 1, -64(1)
138+
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
139+
; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
140+
; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
141+
; ASM32-DAG: rlwinm 3, [[REG2]], 8, 16, 23
142+
; ASM32-DAG: rlwimi 3, [[REG1]], 16, 0, 15
143+
; ASM32-NEXT: bl .test_byval_3Byte
144+
; ASM32-NEXT: nop
143145

144146
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
145147
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
@@ -152,14 +154,14 @@ declare void @test_byval_3Byte(%struct.S3* byval(%struct.S3) align 1)
152154
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
153155

154156
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
155-
; ASM64PWR4: stdu 1, -112(1)
156-
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
157-
; ASM64PWR4-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
158-
; ASM64PWR4-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
159-
; ASM64PWR4-DAG: rldic 3, [[REG2]], 40, 16
160-
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 48, 0
161-
; ASM64PWR4-NEXT: bl .test_byval_3Byte
162-
; ASM64PWR4-NEXT: nop
157+
; ASM64: stdu 1, -112(1)
158+
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
159+
; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
160+
; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
161+
; ASM64-DAG: rldic 3, [[REG2]], 40, 16
162+
; ASM64-DAG: rldimi 3, [[REG1]], 48, 0
163+
; ASM64-NEXT: bl .test_byval_3Byte
164+
; ASM64-NEXT: nop
163165

164166
%struct.S4 = type { [4 x i8] }
165167

@@ -183,12 +185,12 @@ declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1)
183185

184186
; CHECKASM-LABEL: .call_test_byval_4Byte:
185187

186-
; ASM32PWR4: stwu 1, -64(1)
187-
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
188-
; ASM32PWR4-NEXT: lwz 3, 0([[REG]])
189-
; ASM32PWR4-NEXT: bl .test_byval_4Byte
190-
; ASM32PWR4-NEXT: nop
191-
; ASM32PWR4-NEXT: addi 1, 1, 64
188+
; ASM32: stwu 1, -64(1)
189+
; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
190+
; ASM32-NEXT: lwz 3, 0([[REG]])
191+
; ASM32-NEXT: bl .test_byval_4Byte
192+
; ASM32-NEXT: nop
193+
; ASM32-NEXT: addi 1, 1, 64
192194

193195
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
194196
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
@@ -197,10 +199,10 @@ declare void @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1)
197199
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
198200
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
199201

200-
; ASM64PWR4: stdu 1, -112(1)
201-
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
202-
; ASM64PWR4-NEXT: lwz 3, 0([[REG]])
203-
; ASM64PWR4-NEXT: sldi 3, 3, 32
204-
; ASM64PWR4-NEXT: bl .test_byval_4Byte
205-
; ASM64PWR4-NEXT: nop
206-
; ASM64PWR4-NEXT: addi 1, 1, 112
202+
; ASM64: stdu 1, -112(1)
203+
; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
204+
; ASM64-NEXT: lwz 3, 0([[REG]])
205+
; ASM64-NEXT: sldi 3, 3, 32
206+
; ASM64-NEXT: bl .test_byval_4Byte
207+
; ASM64-NEXT: nop
208+
; ASM64-NEXT: addi 1, 1, 112

‎llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

Lines changed: 70 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
1-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
2-
; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
1+
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \
2+
; RUN: -mattr=-altivec -verify-machineinstrs < %s | \
3+
; RUN: FileCheck %s
34

45
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
56
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \
6-
; RUN: FileCheck --check-prefixes=CHECKASM,ASM64PWR4 %s
7+
; RUN: FileCheck --check-prefix=ASM %s
78

89
%struct.S5 = type { [5 x i8] }
910

@@ -19,27 +20,27 @@ declare void @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
1920

2021
; CHECK-LABEL: name: call_test_byval_5Byte{{.*}}
2122

22-
; CHECKASM-LABEL: .call_test_byval_5Byte:
23+
; ASM-LABEL: .call_test_byval_5Byte:
2324

2425
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
25-
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
26-
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
27-
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
28-
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
29-
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
30-
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
31-
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
32-
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
26+
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
27+
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
28+
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
29+
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
30+
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
31+
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
32+
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
33+
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
3334

3435
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
35-
; ASM64PWR4: stdu 1, -112(1)
36-
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
37-
; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
38-
; ASM64PWR4-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
39-
; ASM64PWR4-DAG: rlwinm 3, [[REG2]], 24, 0, 7
40-
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
41-
; ASM64PWR4-NEXT: bl .test_byval_5Byte
42-
; ASM64PWR4-NEXT: nop
36+
; ASM: stdu 1, -112(1)
37+
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
38+
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
39+
; ASM-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
40+
; ASM-DAG: rlwinm 3, [[REG2]], 24, 0, 7
41+
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
42+
; ASM-NEXT: bl .test_byval_5Byte
43+
; ASM-NEXT: nop
4344

4445
%struct.S6 = type { [6 x i8] }
4546

@@ -55,27 +56,27 @@ declare void @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
5556

5657
; CHECK-LABEL: name: call_test_byval_6Byte{{.*}}
5758

58-
; CHECKASM-LABEL: .call_test_byval_6Byte:
59+
; ASM-LABEL: .call_test_byval_6Byte:
5960

6061
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
61-
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
62-
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
63-
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
64-
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
65-
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
66-
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
67-
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
68-
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
62+
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
63+
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
64+
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
65+
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
66+
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
67+
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
68+
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
69+
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
6970

7071
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
71-
; ASM64PWR4: stdu 1, -112(1)
72-
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
73-
; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
74-
; ASM64PWR4-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
75-
; ASM64PWR4-DAG: rlwinm 3, [[REG2]], 16, 0, 15
76-
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
77-
; ASM64PWR4-NEXT: bl .test_byval_6Byte
78-
; ASM64PWR4-NEXT: nop
72+
; ASM: stdu 1, -112(1)
73+
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
74+
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
75+
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
76+
; ASM-DAG: rlwinm 3, [[REG2]], 16, 0, 15
77+
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
78+
; ASM-NEXT: bl .test_byval_6Byte
79+
; ASM-NEXT: nop
7980

8081
%struct.S7 = type { [7 x i8] }
8182

@@ -91,31 +92,31 @@ declare void @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
9192

9293
; CHECK-LABEL: name: call_test_byval_7Byte{{.*}}
9394

94-
; CHECKASM-LABEL: .call_test_byval_7Byte:
95+
; ASM-LABEL: .call_test_byval_7Byte:
9596

9697
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
97-
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
98-
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
99-
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
100-
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
101-
; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
102-
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
103-
; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
104-
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
105-
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
106-
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
98+
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
99+
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
100+
; CHECK-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
101+
; CHECK-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
102+
; CHECK-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
103+
; CHECK-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
104+
; CHECK-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
105+
; CHECK-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
106+
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
107+
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
107108

108109
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
109-
; ASM64PWR4: stdu 1, -112(1)
110-
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
111-
; ASM64PWR4-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
112-
; ASM64PWR4-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
113-
; ASM64PWR4-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
114-
; ASM64PWR4-DAG: rlwinm 3, [[REG3]], 8, 16, 23
115-
; ASM64PWR4-DAG: rlwimi 3, [[REG2]], 16, 0, 15
116-
; ASM64PWR4-DAG: rldimi 3, [[REG1]], 32, 0
117-
; ASM64PWR4-NEXT: bl .test_byval_7Byte
118-
; ASM64PWR4-NEXT: nop
110+
; ASM: stdu 1, -112(1)
111+
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
112+
; ASM-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
113+
; ASM-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
114+
; ASM-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
115+
; ASM-DAG: rlwinm 3, [[REG3]], 8, 16, 23
116+
; ASM-DAG: rlwimi 3, [[REG2]], 16, 0, 15
117+
; ASM-DAG: rldimi 3, [[REG1]], 32, 0
118+
; ASM-NEXT: bl .test_byval_7Byte
119+
; ASM-NEXT: nop
119120

120121
%struct.S8 = type { [8 x i8] }
121122

@@ -131,16 +132,16 @@ declare void @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
131132

132133
; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
133134

134-
; CHECKASM-LABEL: .call_test_byval_8Byte:
135+
; ASM-LABEL: .call_test_byval_8Byte:
135136

136-
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
137-
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
138-
; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
139-
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
140-
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
137+
; CHECK: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
138+
; CHECK-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
139+
; CHECK-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
140+
; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
141+
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
141142

142-
; ASM64PWR4: stdu 1, -112(1)
143-
; ASM64PWR4-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
144-
; ASM64PWR4-NEXT: ld 3, 0([[REGADDR]])
145-
; ASM64PWR4-NEXT: bl .test_byval_8Byte
146-
; ASM64PWR4-NEXT: nop
143+
; ASM: stdu 1, -112(1)
144+
; ASM-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
145+
; ASM-NEXT: ld 3, 0([[REGADDR]])
146+
; ASM-NEXT: bl .test_byval_8Byte
147+
; ASM-NEXT: nop

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