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MIR: Use Register
1 parent 293c521 commit 0aa0d70

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4 files changed

+39
-38
lines changed

4 files changed

+39
-38
lines changed

‎llvm/include/llvm/CodeGen/MIRParser/MIParser.h

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "llvm/ADT/DenseMap.h"
1717
#include "llvm/ADT/StringMap.h"
1818
#include "llvm/CodeGen/MachineMemOperand.h"
19+
#include "llvm/CodeGen/Register.h"
1920
#include "llvm/Support/Allocator.h"
2021

2122
namespace llvm {
@@ -40,8 +41,8 @@ struct VRegInfo {
4041
const TargetRegisterClass *RC;
4142
const RegisterBank *RegBank;
4243
} D;
43-
unsigned VReg;
44-
unsigned PreferredReg = 0;
44+
Register VReg;
45+
Register PreferredReg;
4546
};
4647

4748
using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -55,7 +56,7 @@ struct PerTargetMIParsingState {
5556
StringMap<unsigned> Names2InstrOpCodes;
5657

5758
/// Maps from register names to registers.
58-
StringMap<unsigned> Names2Regs;
59+
StringMap<Register> Names2Regs;
5960

6061
/// Maps from register mask names to register masks.
6162
StringMap<const uint32_t *> Names2RegMasks;
@@ -100,7 +101,7 @@ struct PerTargetMIParsingState {
100101

101102
/// Try to convert a register name to a register number. Return true if the
102103
/// register name is invalid.
103-
bool getRegisterByName(StringRef RegName, unsigned &Reg);
104+
bool getRegisterByName(StringRef RegName, Register &Reg);
104105

105106
/// Check if the given identifier is a name of a register mask.
106107
///
@@ -164,7 +165,7 @@ struct PerFunctionMIParsingState {
164165
PerTargetMIParsingState &Target;
165166

166167
DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
167-
DenseMap<unsigned, VRegInfo *> VRegInfos;
168+
DenseMap<Register, VRegInfo *> VRegInfos;
168169
StringMap<VRegInfo *> VRegInfosNamed;
169170
DenseMap<unsigned, int> FixedStackObjectSlots;
170171
DenseMap<unsigned, int> StackObjectSlots;
@@ -178,7 +179,7 @@ struct PerFunctionMIParsingState {
178179
const SlotMapping &IRSlots,
179180
PerTargetMIParsingState &Target);
180181

181-
VRegInfo &getVRegInfo(unsigned Num);
182+
VRegInfo &getVRegInfo(Register Num);
182183
VRegInfo &getVRegInfoNamed(StringRef RegName);
183184
const Value *getIRValue(unsigned Slot);
184185
};
@@ -216,10 +217,10 @@ bool parseMBBReference(PerFunctionMIParsingState &PFS,
216217
SMDiagnostic &Error);
217218

218219
bool parseRegisterReference(PerFunctionMIParsingState &PFS,
219-
unsigned &Reg, StringRef Src,
220+
Register &Reg, StringRef Src,
220221
SMDiagnostic &Error);
221222

222-
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
223+
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg,
223224
StringRef Src, SMDiagnostic &Error);
224225

225226
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,

‎llvm/lib/CodeGen/MIRParser/MIParser.cpp

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ void PerTargetMIParsingState::initNames2Regs() {
122122
}
123123

124124
bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
125-
unsigned &Reg) {
125+
Register &Reg) {
126126
initNames2Regs();
127127
auto RegInfo = Names2Regs.find(RegName);
128128
if (RegInfo == Names2Regs.end())
@@ -321,7 +321,7 @@ PerFunctionMIParsingState::PerFunctionMIParsingState(MachineFunction &MF,
321321
: MF(MF), SM(&SM), IRSlots(IRSlots), Target(T) {
322322
}
323323

324-
VRegInfo &PerFunctionMIParsingState::getVRegInfo(unsigned Num) {
324+
VRegInfo &PerFunctionMIParsingState::getVRegInfo(Register Num) {
325325
auto I = VRegInfos.insert(std::make_pair(Num, nullptr));
326326
if (I.second) {
327327
MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -426,9 +426,9 @@ class MIParser {
426426
bool parseBasicBlocks();
427427
bool parse(MachineInstr *&MI);
428428
bool parseStandaloneMBB(MachineBasicBlock *&MBB);
429-
bool parseStandaloneNamedRegister(unsigned &Reg);
429+
bool parseStandaloneNamedRegister(Register &Reg);
430430
bool parseStandaloneVirtualRegister(VRegInfo *&Info);
431-
bool parseStandaloneRegister(unsigned &Reg);
431+
bool parseStandaloneRegister(Register &Reg);
432432
bool parseStandaloneStackObject(int &FI);
433433
bool parseStandaloneMDNode(MDNode *&Node);
434434

@@ -439,10 +439,10 @@ class MIParser {
439439
bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
440440
bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
441441

442-
bool parseNamedRegister(unsigned &Reg);
442+
bool parseNamedRegister(Register &Reg);
443443
bool parseVirtualRegister(VRegInfo *&Info);
444444
bool parseNamedVirtualRegister(VRegInfo *&Info);
445-
bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
445+
bool parseRegister(Register &Reg, VRegInfo *&VRegInfo);
446446
bool parseRegisterFlag(unsigned &Flags);
447447
bool parseRegisterClassOrBank(VRegInfo &RegInfo);
448448
bool parseSubRegisterIndex(unsigned &SubReg);
@@ -474,7 +474,7 @@ class MIParser {
474474
bool parseDILocation(MDNode *&Expr);
475475
bool parseMetadataOperand(MachineOperand &Dest);
476476
bool parseCFIOffset(int &Offset);
477-
bool parseCFIRegister(unsigned &Reg);
477+
bool parseCFIRegister(Register &Reg);
478478
bool parseCFIEscapeValues(std::string& Values);
479479
bool parseCFIOperand(MachineOperand &Dest);
480480
bool parseIRBlock(BasicBlock *&BB, const Function &F);
@@ -775,7 +775,7 @@ bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) {
775775
do {
776776
if (Token.isNot(MIToken::NamedRegister))
777777
return error("expected a named register");
778-
unsigned Reg = 0;
778+
Register Reg;
779779
if (parseNamedRegister(Reg))
780780
return true;
781781
lex();
@@ -1083,7 +1083,7 @@ bool MIParser::parseStandaloneMBB(MachineBasicBlock *&MBB) {
10831083
return false;
10841084
}
10851085

1086-
bool MIParser::parseStandaloneNamedRegister(unsigned &Reg) {
1086+
bool MIParser::parseStandaloneNamedRegister(Register &Reg) {
10871087
lex();
10881088
if (Token.isNot(MIToken::NamedRegister))
10891089
return error("expected a named register");
@@ -1107,7 +1107,7 @@ bool MIParser::parseStandaloneVirtualRegister(VRegInfo *&Info) {
11071107
return false;
11081108
}
11091109

1110-
bool MIParser::parseStandaloneRegister(unsigned &Reg) {
1110+
bool MIParser::parseStandaloneRegister(Register &Reg) {
11111111
lex();
11121112
if (Token.isNot(MIToken::NamedRegister) &&
11131113
Token.isNot(MIToken::VirtualRegister))
@@ -1158,7 +1158,7 @@ static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
11581158
}
11591159

11601160
static std::string getRegisterName(const TargetRegisterInfo *TRI,
1161-
unsigned Reg) {
1161+
Register Reg) {
11621162
assert(Register::isPhysicalRegister(Reg) && "expected phys reg");
11631163
return StringRef(TRI->getName(Reg)).lower();
11641164
}
@@ -1258,7 +1258,7 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) {
12581258
return false;
12591259
}
12601260

1261-
bool MIParser::parseNamedRegister(unsigned &Reg) {
1261+
bool MIParser::parseNamedRegister(Register &Reg) {
12621262
assert(Token.is(MIToken::NamedRegister) && "Needs NamedRegister token");
12631263
StringRef Name = Token.stringValue();
12641264
if (PFS.Target.getRegisterByName(Name, Reg))
@@ -1286,7 +1286,7 @@ bool MIParser::parseVirtualRegister(VRegInfo *&Info) {
12861286
return false;
12871287
}
12881288

1289-
bool MIParser::parseRegister(unsigned &Reg, VRegInfo *&Info) {
1289+
bool MIParser::parseRegister(Register &Reg, VRegInfo *&Info) {
12901290
switch (Token.kind()) {
12911291
case MIToken::underscore:
12921292
Reg = 0;
@@ -1480,7 +1480,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
14801480
}
14811481
if (!Token.isRegister())
14821482
return error("expected a register after register flags");
1483-
unsigned Reg;
1483+
Register Reg;
14841484
VRegInfo *RegInfo;
14851485
if (parseRegister(Reg, RegInfo))
14861486
return true;
@@ -2173,10 +2173,10 @@ bool MIParser::parseCFIOffset(int &Offset) {
21732173
return false;
21742174
}
21752175

2176-
bool MIParser::parseCFIRegister(unsigned &Reg) {
2176+
bool MIParser::parseCFIRegister(Register &Reg) {
21772177
if (Token.isNot(MIToken::NamedRegister))
21782178
return error("expected a cfi register");
2179-
unsigned LLVMReg;
2179+
Register LLVMReg;
21802180
if (parseNamedRegister(LLVMReg))
21812181
return true;
21822182
const auto *TRI = MF.getSubtarget().getRegisterInfo();
@@ -2208,7 +2208,7 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) {
22082208
auto Kind = Token.kind();
22092209
lex();
22102210
int Offset;
2211-
unsigned Reg;
2211+
Register Reg;
22122212
unsigned CFIIndex;
22132213
switch (Kind) {
22142214
case MIToken::kw_cfi_same_value:
@@ -2274,7 +2274,7 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) {
22742274
CFIIndex = MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, Reg));
22752275
break;
22762276
case MIToken::kw_cfi_register: {
2277-
unsigned Reg2;
2277+
Register Reg2;
22782278
if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) ||
22792279
parseCFIRegister(Reg2))
22802280
return true;
@@ -2504,7 +2504,7 @@ bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
25042504
while (true) {
25052505
if (Token.isNot(MIToken::NamedRegister))
25062506
return error("expected a named register");
2507-
unsigned Reg;
2507+
Register Reg;
25082508
if (parseNamedRegister(Reg))
25092509
return true;
25102510
lex();
@@ -2530,7 +2530,7 @@ bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
25302530
while (true) {
25312531
if (Token.isNot(MIToken::NamedRegister))
25322532
return error("expected a named register");
2533-
unsigned Reg;
2533+
Register Reg;
25342534
if (parseNamedRegister(Reg))
25352535
return true;
25362536
lex();
@@ -3207,13 +3207,13 @@ bool llvm::parseMBBReference(PerFunctionMIParsingState &PFS,
32073207
}
32083208

32093209
bool llvm::parseRegisterReference(PerFunctionMIParsingState &PFS,
3210-
unsigned &Reg, StringRef Src,
3210+
Register &Reg, StringRef Src,
32113211
SMDiagnostic &Error) {
32123212
return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
32133213
}
32143214

32153215
bool llvm::parseNamedRegisterReference(PerFunctionMIParsingState &PFS,
3216-
unsigned &Reg, StringRef Src,
3216+
Register &Reg, StringRef Src,
32173217
SMDiagnostic &Error) {
32183218
return MIParser(PFS, Error, Src).parseStandaloneNamedRegister(Reg);
32193219
}

‎llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -375,7 +375,7 @@ bool MIRParserImpl::initializeCallSiteInfo(
375375
" is not a call instruction");
376376
MachineFunction::CallSiteInfo CSInfo;
377377
for (auto ArgRegPair : YamlCSInfo.ArgForwardingRegs) {
378-
unsigned Reg = 0;
378+
Register Reg;
379379
if (parseNamedRegisterReference(PFS, Reg, ArgRegPair.Reg.Value, Error))
380380
return error(Error, ArgRegPair.Reg.SourceRange);
381381
CSInfo.emplace_back(Reg, ArgRegPair.ArgNo);
@@ -557,10 +557,10 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
557557

558558
// Parse the liveins.
559559
for (const auto &LiveIn : YamlMF.LiveIns) {
560-
unsigned Reg = 0;
560+
Register Reg;
561561
if (parseNamedRegisterReference(PFS, Reg, LiveIn.Register.Value, Error))
562562
return error(Error, LiveIn.Register.SourceRange);
563-
unsigned VReg = 0;
563+
Register VReg;
564564
if (!LiveIn.VirtualRegister.Value.empty()) {
565565
VRegInfo *Info;
566566
if (parseVirtualRegisterReference(PFS, Info, LiveIn.VirtualRegister.Value,
@@ -576,7 +576,7 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
576576
if (YamlMF.CalleeSavedRegisters) {
577577
SmallVector<MCPhysReg, 16> CalleeSavedRegisters;
578578
for (const auto &RegSource : YamlMF.CalleeSavedRegisters.getValue()) {
579-
unsigned Reg = 0;
579+
Register Reg;
580580
if (parseNamedRegisterReference(PFS, Reg, RegSource.Value, Error))
581581
return error(Error, RegSource.SourceRange);
582582
CalleeSavedRegisters.push_back(Reg);
@@ -594,7 +594,7 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
594594
bool Error = false;
595595
// Create VRegs
596596
auto populateVRegInfo = [&] (const VRegInfo &Info, Twine Name) {
597-
unsigned Reg = Info.VReg;
597+
Register Reg = Info.VReg;
598598
switch (Info.Kind) {
599599
case VRegInfo::UNKNOWN:
600600
error(Twine("Cannot determine class/bank of virtual register ") +
@@ -765,7 +765,7 @@ bool MIRParserImpl::parseCalleeSavedRegister(PerFunctionMIParsingState &PFS,
765765
const yaml::StringValue &RegisterSource, bool IsRestored, int FrameIdx) {
766766
if (RegisterSource.Value.empty())
767767
return false;
768-
unsigned Reg = 0;
768+
Register Reg;
769769
SMDiagnostic Error;
770770
if (parseNamedRegisterReference(PFS, Reg, RegisterSource.Value, Error))
771771
return error(Error, RegisterSource.SourceRange);

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1069,7 +1069,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
10691069

10701070
auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
10711071
// FIXME: Update parseNamedRegsiterReference to take a Register.
1072-
unsigned TempReg;
1072+
Register TempReg;
10731073
if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
10741074
SourceRange = RegName.SourceRange;
10751075
return true;
@@ -1120,7 +1120,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
11201120
return false;
11211121

11221122
if (A->IsRegister) {
1123-
unsigned Reg;
1123+
Register Reg;
11241124
if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
11251125
SourceRange = A->RegisterName.SourceRange;
11261126
return true;

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