@@ -4802,8 +4802,59 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
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SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand (4 ));
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+ const X86InstrInfo *TII =
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+ ((X86TargetMachine&)getTargetMachine ()).getInstrInfo ();
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+
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if (Subtarget->is64Bit ()) {
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- return SDOperand (); // not yet supported
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+ SDOperand OutChains[6 ];
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+
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+ // Large code-model.
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+
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+ const unsigned char JMP64r = TII->getBaseOpcodeFor (X86::JMP64r);
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+ const unsigned char MOV64ri = TII->getBaseOpcodeFor (X86::MOV64ri);
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+
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+ const unsigned char N86R10 =
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+ ((X86RegisterInfo*)RegInfo)->getX86RegNum (X86::R10);
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+ const unsigned char N86R11 =
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+ ((X86RegisterInfo*)RegInfo)->getX86RegNum (X86::R11);
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+
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+ const unsigned char REX_WB = 0x40 | 0x08 | 0x01 ; // REX prefix
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+
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+ // Load the pointer to the nested function into R11.
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+ unsigned OpCode = ((MOV64ri | N86R11) << 8 ) | REX_WB; // movabsq r11
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+ SDOperand Addr = Trmp;
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+ OutChains[0 ] = DAG.getStore (Root, DAG.getConstant (OpCode, MVT::i16 ), Addr,
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+ TrmpSV->getValue (), TrmpSV->getOffset ());
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+
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+ Addr = DAG.getNode (ISD::ADD, MVT::i64 , Trmp, DAG.getConstant (2 , MVT::i64 ));
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+ OutChains[1 ] = DAG.getStore (Root, FPtr, Addr, TrmpSV->getValue (),
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+ TrmpSV->getOffset () + 2 , false , 2 );
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+
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+ // Load the 'nest' parameter value into R10.
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+ // R10 is specified in X86CallingConv.td
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+ OpCode = ((MOV64ri | N86R10) << 8 ) | REX_WB; // movabsq r10
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+ Addr = DAG.getNode (ISD::ADD, MVT::i64 , Trmp, DAG.getConstant (10 , MVT::i64 ));
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+ OutChains[2 ] = DAG.getStore (Root, DAG.getConstant (OpCode, MVT::i16 ), Addr,
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+ TrmpSV->getValue (), TrmpSV->getOffset () + 10 );
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+
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+ Addr = DAG.getNode (ISD::ADD, MVT::i64 , Trmp, DAG.getConstant (12 , MVT::i64 ));
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+ OutChains[3 ] = DAG.getStore (Root, Nest, Addr, TrmpSV->getValue (),
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+ TrmpSV->getOffset () + 12 , false , 2 );
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+
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+ // Jump to the nested function.
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+ OpCode = (JMP64r << 8 ) | REX_WB; // jmpq *...
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+ Addr = DAG.getNode (ISD::ADD, MVT::i64 , Trmp, DAG.getConstant (20 , MVT::i64 ));
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+ OutChains[4 ] = DAG.getStore (Root, DAG.getConstant (OpCode, MVT::i16 ), Addr,
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+ TrmpSV->getValue (), TrmpSV->getOffset () + 20 );
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+
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+ unsigned char ModRM = N86R11 | (4 << 3 ) | (3 << 6 ); // ...r11
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+ Addr = DAG.getNode (ISD::ADD, MVT::i64 , Trmp, DAG.getConstant (22 , MVT::i64 ));
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+ OutChains[5 ] = DAG.getStore (Root, DAG.getConstant (ModRM, MVT::i8 ), Addr,
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+ TrmpSV->getValue (), TrmpSV->getOffset () + 22 );
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+
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+ SDOperand Ops[] =
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+ { Trmp, DAG.getNode (ISD::TokenFactor, MVT::Other, OutChains, 6 ) };
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+ return DAG.getNode (ISD::MERGE_VALUES, Op.Val ->getVTList (), Ops, 2 );
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} else {
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Function *Func = (Function *)
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cast<Function>(cast<SrcValueSDNode>(Op.getOperand (5 ))->getValue ());
@@ -4847,25 +4898,23 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
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break ;
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}
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- const X86InstrInfo *TII =
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- ((X86TargetMachine&)getTargetMachine ()).getInstrInfo ();
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-
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SDOperand OutChains[4 ];
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SDOperand Addr, Disp;
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Addr = DAG.getNode (ISD::ADD, MVT::i32 , Trmp, DAG.getConstant (10 , MVT::i32 ));
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Disp = DAG.getNode (ISD::SUB, MVT::i32 , FPtr, Addr);
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- unsigned char MOV32ri = TII->getBaseOpcodeFor (X86::MOV32ri);
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- unsigned char N86Reg = ((X86RegisterInfo*)RegInfo)->getX86RegNum (NestReg);
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+ const unsigned char MOV32ri = TII->getBaseOpcodeFor (X86::MOV32ri);
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+ const unsigned char N86Reg =
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+ ((X86RegisterInfo*)RegInfo)->getX86RegNum (NestReg);
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OutChains[0 ] = DAG.getStore (Root, DAG.getConstant (MOV32ri|N86Reg, MVT::i8 ),
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Trmp, TrmpSV->getValue (), TrmpSV->getOffset ());
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Addr = DAG.getNode (ISD::ADD, MVT::i32 , Trmp, DAG.getConstant (1 , MVT::i32 ));
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OutChains[1 ] = DAG.getStore (Root, Nest, Addr, TrmpSV->getValue (),
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TrmpSV->getOffset () + 1 , false , 1 );
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- unsigned char JMP = TII->getBaseOpcodeFor (X86::JMP);
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+ const unsigned char JMP = TII->getBaseOpcodeFor (X86::JMP);
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Addr = DAG.getNode (ISD::ADD, MVT::i32 , Trmp, DAG.getConstant (5 , MVT::i32 ));
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OutChains[2 ] = DAG.getStore (Root, DAG.getConstant (JMP, MVT::i8 ), Addr,
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TrmpSV->getValue () + 5 , TrmpSV->getOffset ());
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