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//
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// ===----------------------------------------------------------------------===//
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//
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- // This tablegen backend emits subtarget enumerations.
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+ // This tablegen backend emits subtarget enumerations. The format is in a state
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+ // flux and will be tightened up when integration to scheduling is complete.
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//
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// ===----------------------------------------------------------------------===//
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@@ -62,7 +63,7 @@ void SubtargetEmitter::Enumeration(std::ostream &OS,
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// If bit flags then emit expression (1 << i)
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if (isBits) OS << " = " << " 1 << " << i;
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- // Depending on if more in the list emit comma
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+ // Depending on ' if more in the list' emit comma
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if (++i < N) OS << " ," ;
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OS << " \n " ;
@@ -102,7 +103,7 @@ void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) {
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<< Name
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<< " }" ;
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- // Depending on if more in the list emit comma
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+ // Depending on ' if more in the list' emit comma
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if (++i < N) OS << " ," ;
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OS << " \n " ;
@@ -158,7 +159,7 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) {
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OS << " }" ;
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- // Depending on if more in the list emit comma
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+ // Depending on ' if more in the list' emit comma
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if (++i < N) OS << " ," ;
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OS << " \n " ;
@@ -315,9 +316,9 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS,
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}
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//
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- // EmitProcessData - Generate data for processor itineraries.
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+ // EmitProcessorData - Generate data for processor itineraries.
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//
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- void SubtargetEmitter::EmitProcessData (std::ostream &OS,
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+ void SubtargetEmitter::EmitProcessorData (std::ostream &OS,
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std::vector<std::vector<InstrItinerary> > &ProcList) {
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// Get an iterator for processor itinerary stages
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std::vector<std::vector<InstrItinerary> >::iterator
@@ -362,6 +363,54 @@ void SubtargetEmitter::EmitProcessData(std::ostream &OS,
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// End processor itinerary table
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OS << " };\n " ;
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}
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+
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+ OS << " \n " ;
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+ OS << " static llvm::InstrItinerary NoItineraries[] = {};\n " ;
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+ }
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+
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+ //
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+ // EmitProcessorLookup - generate cpu name to itinerary lookup table.
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+ //
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+ void SubtargetEmitter::EmitProcessorLookup (std::ostream &OS) {
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+ // Gather and sort processor information
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+ std::vector<Record*> ProcessorList =
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+ Records.getAllDerivedDefinitions (" Processor" );
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+ sort (ProcessorList.begin (), ProcessorList.end (), LessRecordFieldName ());
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+
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+ // Begin processor table
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+ OS << " \n " ;
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+ OS << " // Sorted (by key) array of itineraries for CPU subtype.\n "
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+ << " static const llvm::SubtargetInfoKV SubTypeInfoKV[] = {\n " ;
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+
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+ // For each processor
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+ for (unsigned i = 0 , N = ProcessorList.size (); i < N;) {
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+ // Next processor
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+ Record *Processor = ProcessorList[i];
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+
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+ std::string Name = Processor->getValueAsString (" Name" );
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+ std::string ProcItin = Processor->getValueAsDef (" ProcItin" )->getName ();
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+
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+ // Emit as { "cpu", procinit },
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+ OS << " { "
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+ << " \" " << Name << " \" , "
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+ << " (void *)&" << ProcItin;
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+
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+ OS << " }" ;
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+
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+ // Depending on ''if more in the list'' emit comma
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+ if (++i < N) OS << " ," ;
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+
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+ OS << " \n " ;
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+ }
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+
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+ // End processor table
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+ OS << " };\n " ;
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+
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+ // Emit size of table
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+ OS<<" \n enum {\n " ;
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+ OS<<" SubTypeInfoKVSize = sizeof(SubTypeInfoKV)/"
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+ " sizeof(llvm::SubtargetInfoKV)\n " ;
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+ OS<<" };\n " ;
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}
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//
@@ -376,7 +425,9 @@ void SubtargetEmitter::EmitData(std::ostream &OS) {
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// Emit the stage data
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EmitStageData (OS, NItinClasses, ItinClassesMap, ProcList);
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// Emit the processor itinerary data
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- EmitProcessData (OS, ProcList);
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+ EmitProcessorData (OS, ProcList);
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+ // Emit the processor lookup data
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+ EmitProcessorLookup (OS);
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}
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//
@@ -409,6 +460,9 @@ void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) {
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OS << " " << Attribute << " = (Bits & " << Instance << " ) != 0;\n " ;
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}
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+ OS << " \n "
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+ << " InstrItinerary *Itin = (InstrItinerary *)"
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+ " Features.getInfo(SubTypeInfoKV, SubTypeInfoKVSize);\n " ;
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OS << " }\n " ;
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}
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