@@ -1015,7 +1015,7 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
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[(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
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(loadf32 addr:$src))))))]>;
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- def : Pat<(v4f32 (X86vzmovl (memopv4f32 addr:$src))),
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+ def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
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(MOVZSS2PSrm addr:$src)>;
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//===----------------------------------------------------------------------===//
@@ -2273,7 +2273,9 @@ def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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(v2f64 (X86vzmovl (v2f64 (scalar_to_vector
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(loadf64 addr:$src))))))]>;
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- def : Pat<(v2f64 (X86vzmovl (memopv2f64 addr:$src))),
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+ def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
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+ (MOVZSD2PDrm addr:$src)>;
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+ def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
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(MOVZSD2PDrm addr:$src)>;
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def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
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}
@@ -2315,13 +2317,17 @@ def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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[(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
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XS, Requires<[HasSSE2]>;
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- let AddedComplexity = 20 in
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+ let AddedComplexity = 20 in {
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def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2i64 (X86vzmovl
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- (memopv2i64 addr:$src))))]>,
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+ (loadv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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+ def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
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+ (MOVZPQILo2PQIrm addr:$src)>;
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+ }
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+
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//===----------------------------------------------------------------------===//
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// SSE3 Instructions
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//===----------------------------------------------------------------------===//
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