Skip to content

Commit 6011627

Browse files
arsenmarsenm
committed
CodeGen: More conversions to use Register
1 parent d2ef8c1 commit 6011627

30 files changed

+222
-244
lines changed

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 25 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ class TargetRegisterClass {
8181
}
8282

8383
/// Return the specified register in the class.
84-
unsigned getRegister(unsigned i) const {
84+
MCRegister getRegister(unsigned i) const {
8585
return MC->getRegister(i);
8686
}
8787

@@ -315,8 +315,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
315315
/// Returns the Register Class of a physical register of the given type,
316316
/// picking the most sub register class of the right type that contains this
317317
/// physreg.
318-
const TargetRegisterClass *
319-
getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
318+
const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
319+
MVT VT = MVT::Other) const;
320320

321321
/// Return the maximal subclass of the given register class that is
322322
/// allocatable or NULL.
@@ -331,12 +331,12 @@ class TargetRegisterInfo : public MCRegisterInfo {
331331

332332
/// Return the additional cost of using this register instead
333333
/// of other registers in its class.
334-
unsigned getCostPerUse(unsigned RegNo) const {
334+
unsigned getCostPerUse(MCRegister RegNo) const {
335335
return InfoDesc[RegNo].CostPerUse;
336336
}
337337

338338
/// Return true if the register is in the allocation of any register class.
339-
bool isInAllocatableClass(unsigned RegNo) const {
339+
bool isInAllocatableClass(MCRegister RegNo) const {
340340
return InfoDesc[RegNo].inAllocatableClass;
341341
}
342342

@@ -520,8 +520,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
520520

521521
/// Return a super-register of the specified register
522522
/// Reg so its sub-register of index SubIdx is Reg.
523-
unsigned getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
524-
const TargetRegisterClass *RC) const {
523+
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
524+
const TargetRegisterClass *RC) const {
525525
return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
526526
}
527527

@@ -605,8 +605,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
605605
}
606606

607607
/// Debugging helper: dump register in human readable form to dbgs() stream.
608-
static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
609-
const TargetRegisterInfo* TRI = nullptr);
608+
static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
609+
const TargetRegisterInfo *TRI = nullptr);
610610

611611
protected:
612612
/// Overridden by TableGen in targets that have sub-registers.
@@ -745,7 +745,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
745745
const TargetRegisterClass *RC) const = 0;
746746

747747
/// Returns size in bits of a phys/virtual/generic register.
748-
unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
748+
unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
749749

750750
/// Get the weight in units of pressure for this register unit.
751751
virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
@@ -784,20 +784,19 @@ class TargetRegisterInfo : public MCRegisterInfo {
784784
/// independent register allocation hints. Targets that override this
785785
/// function should typically call this default implementation as well and
786786
/// expect to see generic copy hints added.
787-
virtual bool getRegAllocationHints(unsigned VirtReg,
788-
ArrayRef<MCPhysReg> Order,
789-
SmallVectorImpl<MCPhysReg> &Hints,
790-
const MachineFunction &MF,
791-
const VirtRegMap *VRM = nullptr,
792-
const LiveRegMatrix *Matrix = nullptr)
793-
const;
787+
virtual bool
788+
getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
789+
SmallVectorImpl<MCPhysReg> &Hints,
790+
const MachineFunction &MF,
791+
const VirtRegMap *VRM = nullptr,
792+
const LiveRegMatrix *Matrix = nullptr) const;
794793

795794
/// A callback to allow target a chance to update register allocation hints
796795
/// when a register is "changed" (e.g. coalesced) to another register.
797796
/// e.g. On ARM, some virtual registers should target register pairs,
798797
/// if one of pair is coalesced to another register, the allocation hint of
799798
/// the other half of the pair should be changed to point to the new register.
800-
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
799+
virtual void updateRegAllocHint(Register Reg, Register NewReg,
801800
MachineFunction &MF) const {
802801
// Do nothing.
803802
}
@@ -855,7 +854,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
855854
/// spill slot. This tells PEI not to create a new stack frame
856855
/// object for the given register. It should be called only after
857856
/// determineCalleeSaves().
858-
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
857+
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
859858
int &FrameIdx) const {
860859
return false;
861860
}
@@ -892,22 +891,22 @@ class TargetRegisterInfo : public MCRegisterInfo {
892891
/// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
893892
/// before insertion point I.
894893
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
895-
unsigned BaseReg, int FrameIdx,
894+
Register BaseReg, int FrameIdx,
896895
int64_t Offset) const {
897896
llvm_unreachable("materializeFrameBaseRegister does not exist on this "
898897
"target");
899898
}
900899

901900
/// Resolve a frame index operand of an instruction
902901
/// to reference the indicated base register plus offset instead.
903-
virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
902+
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
904903
int64_t Offset) const {
905904
llvm_unreachable("resolveFrameIndex does not exist on this target");
906905
}
907906

908907
/// Determine whether a given base register plus offset immediate is
909908
/// encodable to resolve a frame index.
910-
virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
909+
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
911910
int64_t Offset) const {
912911
llvm_unreachable("isFrameOffsetLegal does not exist on this target");
913912
}
@@ -920,7 +919,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
920919
MachineBasicBlock::iterator I,
921920
MachineBasicBlock::iterator &UseMI,
922921
const TargetRegisterClass *RC,
923-
unsigned Reg) const {
922+
Register Reg) const {
924923
return false;
925924
}
926925

@@ -936,7 +935,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
936935
RegScavenger *RS = nullptr) const = 0;
937936

938937
/// Return the assembly name for \p Reg.
939-
virtual StringRef getRegAsmName(unsigned Reg) const {
938+
virtual StringRef getRegAsmName(MCRegister Reg) const {
940939
// FIXME: We are assuming that the assembly name is equal to the TableGen
941940
// name converted to lower case
942941
//
@@ -973,7 +972,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
973972
virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
974973

975974
/// Mark a register and all its aliases as reserved in the given set.
976-
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
975+
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
977976

978977
/// Returns true if for every register in the set all super registers are part
979978
/// of the set as well.
@@ -1177,7 +1176,7 @@ Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
11771176

11781177
/// Create Printable object to print register classes or register banks
11791178
/// on a \ref raw_ostream.
1180-
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
1179+
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
11811180
const TargetRegisterInfo *TRI);
11821181

11831182
} // end namespace llvm

‎llvm/lib/CodeGen/TargetRegisterInfo.cpp

Lines changed: 13 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,8 @@ bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
7575
return true;
7676
}
7777

78-
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
79-
const {
78+
void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
79+
MCRegister Reg) const {
8080
for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
8181
RegisterSet.set(*AI);
8282
}
@@ -170,7 +170,7 @@ Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
170170
});
171171
}
172172

173-
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
173+
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
174174
const TargetRegisterInfo *TRI) {
175175
return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
176176
if (RegInfo.getRegClassOrNull(Reg))
@@ -207,7 +207,7 @@ TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
207207
/// register of the given type, picking the most sub register class of
208208
/// the right type that contains this physreg.
209209
const TargetRegisterClass *
210-
TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
210+
TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const {
211211
assert(Register::isPhysicalRegister(reg) &&
212212
"reg must be a physical register");
213213

@@ -399,13 +399,10 @@ bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
399399
}
400400

401401
// Compute target-independent register allocator hints to help eliminate copies.
402-
bool
403-
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
404-
ArrayRef<MCPhysReg> Order,
405-
SmallVectorImpl<MCPhysReg> &Hints,
406-
const MachineFunction &MF,
407-
const VirtRegMap *VRM,
408-
const LiveRegMatrix *Matrix) const {
402+
bool TargetRegisterInfo::getRegAllocationHints(
403+
Register VirtReg, ArrayRef<MCPhysReg> Order,
404+
SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
405+
const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
409406
const MachineRegisterInfo &MRI = MF.getRegInfo();
410407
const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
411408
MRI.getRegAllocationHints(VirtReg);
@@ -489,10 +486,11 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
489486
return true;
490487
}
491488

492-
unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
493-
const MachineRegisterInfo &MRI) const {
489+
unsigned
490+
TargetRegisterInfo::getRegSizeInBits(Register Reg,
491+
const MachineRegisterInfo &MRI) const {
494492
const TargetRegisterClass *RC{};
495-
if (Register::isPhysicalRegister(Reg)) {
493+
if (Reg.isPhysical()) {
496494
// The size is not directly available for physical registers.
497495
// Instead, we need to access a register class that contains Reg and
498496
// get the size of that register class.
@@ -536,7 +534,7 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
536534

537535
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
538536
LLVM_DUMP_METHOD
539-
void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
537+
void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
540538
const TargetRegisterInfo *TRI) {
541539
dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
542540
}

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -399,7 +399,7 @@ bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
399399
}
400400

401401
bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
402-
unsigned BaseReg,
402+
Register BaseReg,
403403
int64_t Offset) const {
404404
assert(MI && "Unable to get the legal offset for nil instruction.");
405405
StackOffset SaveOffset(Offset, MVT::i8);
@@ -409,7 +409,7 @@ bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
409409
/// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
410410
/// at the beginning of the basic block.
411411
void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
412-
unsigned BaseReg,
412+
Register BaseReg,
413413
int FrameIdx,
414414
int64_t Offset) const {
415415
MachineBasicBlock::iterator Ins = MBB->begin();
@@ -430,7 +430,7 @@ void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
430430
.addImm(Shifter);
431431
}
432432

433-
void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
433+
void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
434434
int64_t Offset) const {
435435
// ARM doesn't need the general 64-bit offsets
436436
StackOffset Off(Offset, MVT::i8);

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,12 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
9696
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
9797

9898
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
99-
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
99+
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
100100
int64_t Offset) const override;
101-
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
101+
void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg,
102102
int FrameIdx,
103103
int64_t Offset) const override;
104-
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
104+
void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
105105
int64_t Offset) const override;
106106
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
107107
unsigned FIOperandNum,

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -386,7 +386,7 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
386386
}
387387

388388
void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
389-
unsigned BaseReg,
389+
Register BaseReg,
390390
int FrameIdx,
391391
int64_t Offset) const {
392392
MachineBasicBlock::iterator Ins = MBB->begin();
@@ -420,7 +420,7 @@ void SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
420420
.addImm(0); // clamp bit
421421
}
422422

423-
void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
423+
void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
424424
int64_t Offset) const {
425425
const SIInstrInfo *TII = ST.getInstrInfo();
426426

@@ -457,7 +457,7 @@ void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
457457
}
458458

459459
bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
460-
unsigned BaseReg,
460+
Register BaseReg,
461461
int64_t Offset) const {
462462
if (!SIInstrInfo::isMUBUF(*MI))
463463
return false;
@@ -1270,7 +1270,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
12701270
}
12711271
}
12721272

1273-
StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
1273+
StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const {
12741274
return AMDGPUInstPrinter::getRegisterName(Reg);
12751275
}
12761276

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -81,14 +81,14 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
8181

8282
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
8383

84-
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
85-
unsigned BaseReg, int FrameIdx,
84+
void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg,
85+
int FrameIdx,
8686
int64_t Offset) const override;
8787

88-
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
88+
void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
8989
int64_t Offset) const override;
9090

91-
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
91+
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
9292
int64_t Offset) const override;
9393

9494
const TargetRegisterClass *getPointerRegClass(
@@ -110,7 +110,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
110110
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
111111
int FI, RegScavenger *RS) const;
112112

113-
StringRef getRegAsmName(unsigned Reg) const override;
113+
StringRef getRegAsmName(MCRegister Reg) const override;
114114

115115
unsigned getHWRegIndex(MCRegister Reg) const {
116116
return getEncodingValue(Reg) & 0xff;

0 commit comments

Comments
 (0)