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kaz7Simon Moll
kaz7
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Simon Moll
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[VE] Update shift operation instructions
Summary: Changing all mnemonic to match assembly instructions to simplify mnemonic naming rules. This time update all shift operation instructions. This also corrects instruction's operation kinds. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D78468
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‎llvm/lib/Target/VE/VEInstrInfo.td

Lines changed: 56 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@ def uimm1 : Operand<i32>, PatLeaf<(imm), [{
3232
def uimm6 : Operand<i32>, PatLeaf<(imm), [{
3333
return isUInt<6>(N->getZExtValue()); }]>;
3434

35+
// uimm7 - Generic immediate value.
36+
def uimm7 : Operand<i32>, PatLeaf<(imm), [{
37+
return isUInt<7>(N->getZExtValue()); }]>;
38+
3539
// simm7 - Generic immediate value.
3640
def LO7 : SDNodeXForm<imm, [{
3741
return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
@@ -423,69 +427,27 @@ multiclass RRFm<string opcStr, bits<8>opc,
423427
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, mOp, null_frag>,
424428
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, mOp, null_frag>;
425429

426-
// Multiclass for RR type instructions
427-
// Used by sra, sla, sll, and similar instructions
428-
// The order of operands are "$sx, $sz, $sy"
429-
430+
// Generic RR multiclass for shift instructions with 2 arguments.
431+
// e.g. SLL, SRL, SLAWSX, and etc.
432+
let hasSideEffects = 0 in
430433
multiclass RRIm<string opcStr, bits<8>opc,
431434
RegisterClass RC, ValueType Ty,
432-
Operand immOp, Operand immOp2,
433-
SDPatternOperator OpNode=null_frag> {
434-
def rr : RR<
435-
opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),
436-
!strconcat(opcStr, " $sx, $sz, $sy"),
437-
[(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]> {
438-
let cy = 1;
439-
let cz = 1;
440-
let hasSideEffects = 0;
441-
}
442-
def ri : RR<
443-
opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy),
444-
!strconcat(opcStr, " $sx, $sz, $sy"),
445-
[(set Ty:$sx, (OpNode Ty:$sz, (i32 simm7:$sy)))]> {
446-
let cy = 0;
447-
let cz = 1;
448-
let hasSideEffects = 0;
449-
}
450-
def rm0 : RR<
451-
opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy),
452-
!strconcat(opcStr, " $sx, (${sz})0, $sy")> {
453-
let cy = 1;
454-
let cz = 0;
455-
let sz{6} = 1;
456-
let hasSideEffects = 0;
457-
}
458-
def rm1 : RR<
459-
opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy),
460-
!strconcat(opcStr, " $sx, (${sz})1, $sy")> {
461-
let cy = 1;
462-
let cz = 0;
463-
let hasSideEffects = 0;
464-
}
465-
def im0 : RR<
466-
opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy),
467-
!strconcat(opcStr, " $sx, (${sz})0, $sy")> {
468-
let cy = 0;
469-
let cz = 0;
470-
let sz{6} = 1;
471-
let hasSideEffects = 0;
472-
}
473-
def im1 : RR<
474-
opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy),
475-
!strconcat(opcStr, " $sx, (${sz})1, $sy")> {
476-
let cy = 0;
477-
let cz = 0;
478-
let hasSideEffects = 0;
479-
}
480-
def zi : RR<
481-
opc, (outs RC:$sx), (ins immOp:$sy),
482-
!strconcat(opcStr, " $sx, $sy"),
483-
[(set Ty:$sx, (OpNode 0, (i32 simm7:$sy)))]> {
484-
let cy = 0;
485-
let cz = 0;
486-
let sz = 0;
487-
let hasSideEffects = 0;
488-
}
435+
SDPatternOperator OpNode = null_frag> {
436+
def rr : RR<opc, (outs RC:$sx), (ins RC:$sz, I32:$sy),
437+
!strconcat(opcStr, " $sx, $sz, $sy"),
438+
[(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]>;
439+
let cz = 0 in
440+
def mr : RR<opc, (outs RC:$sx), (ins mimm:$sz, I32:$sy),
441+
!strconcat(opcStr, " $sx, $sz, $sy"),
442+
[(set Ty:$sx, (OpNode (Ty mimm:$sz), i32:$sy))]>;
443+
let cy = 0 in
444+
def ri : RR<opc, (outs RC:$sx), (ins RC:$sz, uimm7:$sy),
445+
!strconcat(opcStr, " $sx, $sz, $sy"),
446+
[(set Ty:$sx, (OpNode Ty:$sz, (i32 uimm7:$sy)))]>;
447+
let cy = 0, cz = 0 in
448+
def mi : RR<opc, (outs RC:$sx), (ins mimm:$sz, uimm7:$sy),
449+
!strconcat(opcStr, " $sx, $sz, $sy"),
450+
[(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
489451
}
490452

491453
// Generic RR multiclass with an argument.
@@ -898,23 +860,32 @@ let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>;
898860
let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>;
899861
let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>;
900862

901-
// 5.3.2.4 Shift Instructions
863+
//-----------------------------------------------------------------------------
864+
// Section 8.6 - Shift Operation Instructions
865+
//-----------------------------------------------------------------------------
902866

903-
let cx = 0 in
904-
defm SRAX : RRIm<"sra.l", 0x77, I64, i64, simm7, uimm6, sra>;
905-
let cx = 0 in
906-
defm SRA : RRIm<"sra.w.sx", 0x76, I32, i32, simm7, uimm6, sra>;
907-
let cx = 1 in
908-
defm SRAU : RRIm<"sra.w.zx", 0x76, I32, i32, simm7, uimm6>;
867+
// Section 8.6.1 - SLL (Shift Left Logical)
868+
defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
909869

910-
let cx = 0 in
911-
defm SLL : RRIm<"sll", 0x65, I64, i64, simm7, uimm6, shl>;
912-
let cx = 0 in
913-
defm SLA : RRIm<"sla.w.sx", 0x66, I32, i32, simm7, uimm6, shl>;
914-
let cx = 1 in
915-
defm SLAU : RRIm<"sla.w.zx", 0x66, I32, i32, simm7, uimm6>;
916-
let cx = 0 in
917-
defm SRL : RRIm<"srl", 0x75, I64, i64, simm7, uimm6, srl>;
870+
// Section 8.6.2 - SLD (Shift Left Double)
871+
872+
// Section 8.6.3 - SRL (Shift Right Logical)
873+
defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
874+
875+
// Section 8.6.4 - SRD (Shift Right Double)
876+
877+
// Section 8.6.5 - SLA (Shift Left Arithmetic)
878+
defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
879+
let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
880+
881+
// Section 8.6.6 - SLAX (Shift Left Arithmetic)
882+
883+
// Section 8.6.7 - SRA (Shift Right Arithmetic)
884+
defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
885+
let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>;
886+
887+
// Section 8.6.8 - SRAX (Shift Right Arithmetic)
888+
defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>;
918889

919890
def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
920891
(EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
@@ -1113,27 +1084,27 @@ def : Pat<(f64 fpimm:$val),
11131084

11141085
// Cast to i1
11151086
def : Pat<(sext_inreg I32:$src, i1),
1116-
(SRAri (SLAri $src, 31), 31)>;
1087+
(SRAWSXri (SLAWSXri $src, 31), 31)>;
11171088
def : Pat<(sext_inreg I64:$src, i1),
1118-
(SRAXri (SLLri $src, 63), 63)>;
1089+
(SRALri (SLLri $src, 63), 63)>;
11191090

11201091
// Cast to i8
11211092
def : Pat<(sext_inreg I32:$src, i8),
1122-
(SRAri (SLAri $src, 24), 24)>;
1093+
(SRAWSXri (SLAWSXri $src, 24), 24)>;
11231094
def : Pat<(sext_inreg I64:$src, i8),
1124-
(SRAXri (SLLri $src, 56), 56)>;
1095+
(SRALri (SLLri $src, 56), 56)>;
11251096
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),
1126-
(EXTRACT_SUBREG (SRAXri (SLLri $src, 56), 56), sub_i32)>;
1097+
(EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;
11271098
def : Pat<(and (trunc i64:$src), 0xff),
11281099
(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>;
11291100

11301101
// Cast to i16
11311102
def : Pat<(sext_inreg I32:$src, i16),
1132-
(SRAri (SLAri $src, 16), 16)>;
1103+
(SRAWSXri (SLAWSXri $src, 16), 16)>;
11331104
def : Pat<(sext_inreg I64:$src, i16),
1134-
(SRAXri (SLLri $src, 48), 48)>;
1105+
(SRALri (SLLri $src, 48), 48)>;
11351106
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),
1136-
(EXTRACT_SUBREG (SRAXri (SLLri $src, 48), 48), sub_i32)>;
1107+
(EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;
11371108
def : Pat<(and (trunc i64:$src), 0xffff),
11381109
(AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>;
11391110

@@ -1553,7 +1524,7 @@ def : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>;
15531524
def : Pat<(i64 (bitconvert f64:$src)), (COPY_TO_REGCLASS $src, I64)>;
15541525

15551526
def : Pat<(i32 (bitconvert f32:$op)),
1556-
(EXTRACT_SUBREG (SRAXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1527+
(EXTRACT_SUBREG (SRALri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
15571528
$op, sub_f32), 32), sub_i32)>;
15581529
def : Pat<(f32 (bitconvert i32:$op)),
15591530
(EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),

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