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Approved by Evan:
$ svn merge -c 113297 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113297 into '.': U lib/Target/ARM/Thumb2SizeReduction.cpp $ svn merge -c 113322 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113322 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMInstrVFP.td U lib/Target/ARM/ARMInstrFormats.td $ svn merge -c 113365 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113365 into '.': U lib/Target/ARM/ARMBaseRegisterInfo.cpp $ svn merge -c 113366 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113366 into '.': G lib/Target/ARM/ARMBaseRegisterInfo.cpp $ svn merge -c 113394 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113394 into '.': G lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm-svn: 113540
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5 files changed

+42
-20
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5 files changed

+42
-20
lines changed

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -667,8 +667,14 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
667667
}
668668

669669
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
670+
const MachineFrameInfo *MFI = MF.getFrameInfo();
670671
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
671-
return (RealignStack && !AFI->isThumb1OnlyFunction());
672+
// We can't realign the stack if:
673+
// 1. Dynamic stack realignment is explicitly disabled,
674+
// 2. This is a Thumb1 function (it's not useful, so we don't bother), or
675+
// 3. There are VLAs in the function and the base pointer is disabled.
676+
return (RealignStack && !AFI->isThumb1OnlyFunction() &&
677+
(!MFI->hasVarSizedObjects() || EnableBasePointer));
672678
}
673679

674680
bool ARMBaseRegisterInfo::
@@ -1057,8 +1063,11 @@ ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
10571063
if (isFixed) {
10581064
FrameReg = getFrameRegister(MF);
10591065
Offset = FPOffset;
1060-
} else if (MFI->hasVarSizedObjects())
1066+
} else if (MFI->hasVarSizedObjects()) {
1067+
assert(hasBasePointer(MF) &&
1068+
"VLAs and dynamic stack alignment, but missing base pointer!");
10611069
FrameReg = BasePtr;
1070+
}
10621071
return Offset;
10631072
}
10641073

@@ -1068,7 +1077,7 @@ ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
10681077
// there are VLAs (and thus the SP isn't reliable as a base).
10691078
if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
10701079
FrameReg = getFrameRegister(MF);
1071-
Offset = FPOffset;
1080+
return FPOffset;
10721081
} else if (MFI->hasVarSizedObjects()) {
10731082
assert(hasBasePointer(MF) && "missing base pointer!");
10741083
// Use the base register since we have it.
@@ -1078,12 +1087,12 @@ ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
10781087
// out of range references.
10791088
if (FPOffset >= -255 && FPOffset < 0) {
10801089
FrameReg = getFrameRegister(MF);
1081-
Offset = FPOffset;
1090+
return FPOffset;
10821091
}
10831092
} else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
10841093
// Otherwise, use SP or FP, whichever is closer to the stack slot.
10851094
FrameReg = getFrameRegister(MF);
1086-
Offset = FPOffset;
1095+
return FPOffset;
10871096
}
10881097
}
10891098
// Use the base pointer if we have one.
@@ -1887,7 +1896,8 @@ emitPrologue(MachineFunction &MF) const {
18871896
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
18881897
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
18891898

1890-
// If we need dynamic stack realignment, do it here.
1899+
// If we need dynamic stack realignment, do it here. Be paranoid and make
1900+
// sure if we also have VLAs, we have a base pointer for frame access.
18911901
if (needsStackRealignment(MF)) {
18921902
unsigned MaxAlign = MFI->getMaxAlignment();
18931903
assert (!AFI->isThumb1OnlyFunction());

‎llvm/lib/Target/ARM/ARMInstrFormats.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1332,9 +1332,9 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
13321332
}
13331333

13341334
// Load / store multiple
1335-
class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1335+
class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
13361336
string asm, string cstr, list<dag> pattern>
1337-
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1337+
: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
13381338
VFPLdStMulFrm, itin, asm, cstr, pattern> {
13391339
// TODO: Mark the instructions with the appropriate subtarget info.
13401340
let Inst{27-25} = 0b110;
@@ -1344,9 +1344,9 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
13441344
let D = VFPNeonDomain;
13451345
}
13461346

1347-
class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1347+
class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
13481348
string asm, string cstr, list<dag> pattern>
1349-
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
1349+
: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
13501350
VFPLdStMulFrm, itin, asm, cstr, pattern> {
13511351
// TODO: Mark the instructions with the appropriate subtarget info.
13521352
let Inst{27-25} = 0b110;

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ def nModImm : Operand<i32> {
133133
// This is equivalent to VLDMD except that it has a Q register operand
134134
// instead of a pair of D registers.
135135
def VLDMQ
136-
: AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
136+
: AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
137137
IndexModeNone, IIC_fpLoadm,
138138
"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
139139
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
@@ -151,7 +151,7 @@ def VLD1q
151151
// This is equivalent to VSTMD except that it has a Q register operand
152152
// instead of a pair of D registers.
153153
def VSTMQ
154-
: AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
154+
: AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
155155
IndexModeNone, IIC_fpStorem,
156156
"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
157157
[(store (v2f64 QPR:$src), addrmode4:$addr)]>;

‎llvm/lib/Target/ARM/ARMInstrVFP.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -77,27 +77,27 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
7777
//
7878

7979
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
80-
def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
80+
def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
8181
variable_ops), IndexModeNone, IIC_fpLoadm,
8282
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
8383
let Inst{20} = 1;
8484
}
8585

86-
def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
86+
def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
8787
variable_ops), IndexModeNone, IIC_fpLoadm,
8888
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
8989
let Inst{20} = 1;
9090
}
9191

92-
def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
92+
def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
9393
reglist:$dsts, variable_ops),
9494
IndexModeUpd, IIC_fpLoadm,
9595
"vldm${addr:submode}${p}\t$addr!, $dsts",
9696
"$addr.addr = $wb", []> {
9797
let Inst{20} = 1;
9898
}
9999

100-
def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
100+
def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
101101
reglist:$dsts, variable_ops),
102102
IndexModeUpd, IIC_fpLoadm,
103103
"vldm${addr:submode}${p}\t$addr!, $dsts",
@@ -107,27 +107,27 @@ def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
107107
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
108108

109109
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
110-
def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
110+
def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
111111
variable_ops), IndexModeNone, IIC_fpStorem,
112112
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
113113
let Inst{20} = 0;
114114
}
115115

116-
def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
116+
def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
117117
variable_ops), IndexModeNone, IIC_fpStorem,
118118
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
119119
let Inst{20} = 0;
120120
}
121121

122-
def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
122+
def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
123123
reglist:$srcs, variable_ops),
124124
IndexModeUpd, IIC_fpStorem,
125125
"vstm${addr:submode}${p}\t$addr!, $srcs",
126126
"$addr.addr = $wb", []> {
127127
let Inst{20} = 0;
128128
}
129129

130-
def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
130+
def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
131131
reglist:$srcs, variable_ops),
132132
IndexModeUpd, IIC_fpStorem,
133133
"vstm${addr:submode}${p}\t$addr!, $srcs",

‎llvm/lib/Target/ARM/Thumb2SizeReduction.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -315,6 +315,18 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
315315
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
316316
if (!isARMLowRegister(BaseReg) || Mode != ARM_AM::ia)
317317
return false;
318+
// For the non-writeback version (this one), the base register must be
319+
// one of the registers being loaded.
320+
bool isOK = false;
321+
for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
322+
if (MI->getOperand(i).getReg() == BaseReg) {
323+
isOK = true;
324+
break;
325+
}
326+
}
327+
if (!isOK)
328+
return false;
329+
318330
OpNum = 0;
319331
isLdStMul = true;
320332
break;

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