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Commit db39362

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Dale Johannesen
committed
Fill in some missing DL propagation in getNode()s.
llvm-svn: 63595
1 parent 143a2c3 commit db39362

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+24
-22
lines changed

1 file changed

+24
-22
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llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 24 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -854,8 +854,7 @@ SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
854854
SDValue NegOneElt =
855855
getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT);
856856
std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
857-
NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
858-
&NegOnes[0], NegOnes.size());
857+
NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size());
859858
} else {
860859
NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
861860
}
@@ -2150,10 +2149,11 @@ bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
21502149
/// element of the result of the vector shuffle.
21512150
SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
21522151
MVT VT = N->getValueType(0);
2152+
DebugLoc dl = N->getDebugLoc();
21532153
SDValue PermMask = N->getOperand(2);
21542154
SDValue Idx = PermMask.getOperand(i);
21552155
if (Idx.getOpcode() == ISD::UNDEF)
2156-
return getNode(ISD::UNDEF, VT.getVectorElementType());
2156+
return getNode(ISD::UNDEF, dl, VT.getVectorElementType());
21572157
unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
21582158
unsigned NumElems = PermMask.getNumOperands();
21592159
SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
@@ -2167,7 +2167,7 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
21672167
}
21682168
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
21692169
return (Index == 0) ? V.getOperand(0)
2170-
: getNode(ISD::UNDEF, VT.getVectorElementType());
2170+
: getNode(ISD::UNDEF, dl, VT.getVectorElementType());
21712171
if (V.getOpcode() == ISD::BUILD_VECTOR)
21722172
return V.getOperand(Index);
21732173
if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
@@ -2301,7 +2301,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23012301
Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
23022302
if (Operand.getValueType() == VT) return Operand; // noop conversion.
23032303
if (Operand.getOpcode() == ISD::UNDEF)
2304-
return getNode(ISD::UNDEF, VT);
2304+
return getNode(ISD::UNDEF, DL, VT);
23052305
break;
23062306
case ISD::SIGN_EXTEND:
23072307
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2310,7 +2310,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23102310
assert(Operand.getValueType().bitsLT(VT)
23112311
&& "Invalid sext node, dst < src!");
23122312
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2313-
return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2313+
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
23142314
break;
23152315
case ISD::ZERO_EXTEND:
23162316
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2319,7 +2319,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23192319
assert(Operand.getValueType().bitsLT(VT)
23202320
&& "Invalid zext node, dst < src!");
23212321
if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2322-
return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0));
2322+
return getNode(ISD::ZERO_EXTEND, DL, VT,
2323+
Operand.getNode()->getOperand(0));
23232324
break;
23242325
case ISD::ANY_EXTEND:
23252326
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2329,7 +2330,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23292330
&& "Invalid anyext node, dst < src!");
23302331
if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
23312332
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
2332-
return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2333+
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
23332334
break;
23342335
case ISD::TRUNCATE:
23352336
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2338,14 +2339,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23382339
assert(Operand.getValueType().bitsGT(VT)
23392340
&& "Invalid truncate node, src < dst!");
23402341
if (OpOpcode == ISD::TRUNCATE)
2341-
return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
2342+
return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
23422343
else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
23432344
OpOpcode == ISD::ANY_EXTEND) {
23442345
// If the source is smaller than the dest, we still need an extend.
23452346
if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
2346-
return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
2347+
return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
23472348
else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
2348-
return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
2349+
return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
23492350
else
23502351
return Operand.getNode()->getOperand(0);
23512352
}
@@ -2356,16 +2357,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23562357
&& "Cannot BIT_CONVERT between types of different sizes!");
23572358
if (VT == Operand.getValueType()) return Operand; // noop conversion.
23582359
if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
2359-
return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0));
2360+
return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
23602361
if (OpOpcode == ISD::UNDEF)
2361-
return getNode(ISD::UNDEF, VT);
2362+
return getNode(ISD::UNDEF, DL, VT);
23622363
break;
23632364
case ISD::SCALAR_TO_VECTOR:
23642365
assert(VT.isVector() && !Operand.getValueType().isVector() &&
23652366
VT.getVectorElementType() == Operand.getValueType() &&
23662367
"Illegal SCALAR_TO_VECTOR node!");
23672368
if (OpOpcode == ISD::UNDEF)
2368-
return getNode(ISD::UNDEF, VT);
2369+
return getNode(ISD::UNDEF, DL, VT);
23692370
// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
23702371
if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
23712372
isa<ConstantSDNode>(Operand.getOperand(1)) &&
@@ -2376,14 +2377,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
23762377
case ISD::FNEG:
23772378
// -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
23782379
if (UnsafeFPMath && OpOpcode == ISD::FSUB)
2379-
return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1),
2380+
return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
23802381
Operand.getNode()->getOperand(0));
23812382
if (OpOpcode == ISD::FNEG) // --X -> X
23822383
return Operand.getNode()->getOperand(0);
23832384
break;
23842385
case ISD::FABS:
23852386
if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2386-
return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0));
2387+
return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
23872388
break;
23882389
}
23892390

@@ -2473,7 +2474,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
24732474
N2.getOpcode() == ISD::BUILD_VECTOR) {
24742475
SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
24752476
Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
2476-
return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
2477+
return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
24772478
}
24782479
break;
24792480
case ISD::AND:
@@ -2599,7 +2600,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
25992600
case ISD::EXTRACT_VECTOR_ELT:
26002601
// EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
26012602
if (N1.getOpcode() == ISD::UNDEF)
2602-
return getNode(ISD::UNDEF, VT);
2603+
return getNode(ISD::UNDEF, DL, VT);
26032604

26042605
// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
26052606
// expanding copies of large vectors from registers.
@@ -2608,7 +2609,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
26082609
N1.getNumOperands() > 0) {
26092610
unsigned Factor =
26102611
N1.getOperand(0).getValueType().getVectorNumElements();
2611-
return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
2612+
return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
26122613
N1.getOperand(N2C->getZExtValue() / Factor),
26132614
getConstant(N2C->getZExtValue() % Factor,
26142615
N2.getValueType()));
@@ -2629,7 +2630,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
26292630
// the original vector.
26302631
else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
26312632
isa<ConstantSDNode>(N2))
2632-
return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
2633+
return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
26332634
}
26342635
break;
26352636
case ISD::EXTRACT_ELEMENT:
@@ -2990,7 +2991,8 @@ static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG,
29902991
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
29912992
SelectionDAG &DAG) {
29922993
MVT VT = Base.getValueType();
2993-
return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
2994+
return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(),
2995+
VT, Base, DAG.getConstant(Offset, VT));
29942996
}
29952997

29962998
/// isMemSrcFromString - Returns true if memcpy source is a string constant.
@@ -4932,7 +4934,7 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
49324934
MVT VT1, MVT VT2, MVT VT3,
49334935
const SDValue *Ops, unsigned NumOps) {
49344936
const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
4935-
return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
4937+
return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode();
49364938
}
49374939

49384940
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,

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