Skip to content

Commit f5a812c

Browse files
committed
Revert 3ce0ad1 Die to breakage in check-lld.
Requested-by: Nico Weber
1 parent 8aad119 commit f5a812c

File tree

6 files changed

+40
-15
lines changed

6 files changed

+40
-15
lines changed

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,8 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
7171
// Name Offset (bits) Size (bits) Flags
7272
{"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
7373
{"fixup_t2_ldst_pcrel_12", 0, 32,
74-
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
74+
MCFixupKindInfo::FKF_IsPCRel |
75+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
7576
{"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
7677
{"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
7778
{"fixup_t2_pcrel_10", 0, 32,
@@ -81,10 +82,12 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
8182
{"fixup_t2_pcrel_9", 0, 32,
8283
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
8384
{"fixup_thumb_adr_pcrel_10", 0, 8,
84-
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
85+
MCFixupKindInfo::FKF_IsPCRel |
86+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
8587
{"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
8688
{"fixup_t2_adr_pcrel_12", 0, 32,
87-
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
89+
MCFixupKindInfo::FKF_IsPCRel |
90+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
8891
{"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
8992
{"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
9093
{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
@@ -116,8 +119,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
116119
{"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
117120
{"fixup_bfcsel_else_target", 0, 32, 0},
118121
{"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
119-
{"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
120-
};
122+
{"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
121123
const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
122124
// This table *must* be in the order that the fixup_* kinds are defined in
123125
// ARMFixupKinds.h.

llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,13 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
147147
default:
148148
return ELF::R_ARM_THM_CALL;
149149
}
150+
case ARM::fixup_thumb_adr_pcrel_10:
151+
case ARM::fixup_arm_thumb_cp:
152+
return ELF::R_ARM_THM_PC8;
153+
case ARM::fixup_t2_adr_pcrel_12:
154+
return ELF::R_ARM_THM_ALU_PREL_11_0;
155+
case ARM::fixup_t2_ldst_pcrel_12:
156+
return ELF::R_ARM_THM_PC12;
150157
case ARM::fixup_bf_target:
151158
return ELF::R_ARM_THM_BF16;
152159
case ARM::fixup_bfc_target:

llvm/test/MC/ARM/pcrel-global-rel.s

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
@ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
2+
@ RUN: llvm-readobj -r %t
3+
4+
@ Check that for ELF targets we generate a relocation for a within section
5+
@ pc-relative reference to a global symbol as it may be interposed and we won't
6+
@ know till link time whether this is possible.
7+
.thumb
8+
.thumb_func
9+
10+
.globl bar
11+
bar:
12+
adr r0, bar @ thumb_adr_pcrel_10
13+
adr.w r0, bar @ t2_adr_pcrel_12
14+
ldr.w pc, bar @ t2_ldst_pcrel_12
15+
16+
@ CHECK: 0x0 R_ARM_THM_ALU_PREL_11_0 bar 0x0
17+
@ CHECK-NEXT: 0x4 R_ARM_THM_ALU_PREL_11_0 bar 0x0
18+
@ CHECK-NEXT: 0x8 R_ARM_THM_PC12 bar 0x0

llvm/test/MC/ARM/pcrel-global.s

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,3 @@ vldr d0, foo @ arm_pcrel_10
1111
adr r2, foo @ arm_adr_pcrel_12
1212
ldr r0, foo @ arm_ldst_pcrel_12
1313

14-
.thumb
15-
.thumb_func
16-
17-
.globl bar
18-
bar:
19-
adr r0, bar @ thumb_adr_pcrel_10
20-
adr.w r0, bar @ t2_adr_pcrel_12
21-
ldr.w pc, bar @ t2_ldst_pcrel_12

llvm/test/MC/ARM/thumb1-relax-adr.s

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11
@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
22
@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
3-
@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
3+
@ RUN: llvm-mc -triple thumbv6m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T1 %s
4+
@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T2 %s
45

56
.global func1
67
_func1:
78
adr r0, _func2
89
@ CHECK-ERROR: unsupported relocation on symbol
10+
@ CHECK-ELF-T1: 0x0 R_ARM_THM_PC8 _func2 0x0
11+
@ CHECK-ELF-T2: 0x0 R_ARM_THM_ALU_PREL_11_0 _func2 0x0
Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11
@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
22
@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
3-
@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
3+
@ RUN: llvm-mc -triple thumbv6m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T1 %s
4+
@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T2 %s
45

56
.global func1
67
_func1:
78
ldr r0, _func2
89
@ CHECK-ERROR: unsupported relocation on symbol
10+
@ CHECK-ELF-T1: 0x0 R_ARM_THM_PC8 _func2 0x0
11+
@ CHECK-ELF-T2: 0x0 R_ARM_THM_PC12 _func2 0x0

0 commit comments

Comments
 (0)