Revert "[ARM][MVE] Sink vector shift operand"

This reverts commit e0b9666.

Instruction selection is failing with expensive checks.

Author: Sam Parker

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -11814,8 +11814,7 @@ static SDValue PerformADDCombine(SDNode *N,
 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
 ///
 static SDValue PerformSUBCombine(SDNode *N,
-                                 TargetLowering::DAGCombinerInfo &DCI,
-                                 const ARMSubtarget *Subtarget) {
+                                 TargetLowering::DAGCombinerInfo &DCI) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
@@ -11824,27 +11823,7 @@ static SDValue PerformSUBCombine(SDNode *N,
     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI))
       return Result;
 
-  if (!Subtarget->hasMVEIntegerOps() || !N->getValueType(0).isVector())
-    return SDValue();
-
-  // Fold (sub (ARMvmovImm 0), (ARMvdup x)) -> (ARMvdup (sub 0, x))
-  // so that we can readily pattern match more mve instructions which can use
-  // a scalar operand.
-  SDValue VDup = N->getOperand(1);
-  if (VDup->getOpcode() != ARMISD::VDUP)
-    return SDValue();
-
-  SDValue VMov = N->getOperand(0);
-  if (VMov->getOpcode() == ISD::BITCAST)
-    VMov = VMov->getOperand(0);
-
-  if (VMov->getOpcode() != ARMISD::VMOVIMM || !isZeroVector(VMov))
-    return SDValue();
-
-  SDLoc dl(N);
-  SDValue Negate = DCI.DAG.getNode(ISD::SUB, dl, MVT::i32, VMov->getOperand(0),
-                                   VDup->getOperand(0));
-  return DCI.DAG.getNode(ARMISD::VDUP, dl, N->getValueType(0), Negate);
+  return SDValue();
 }
 
 /// PerformVMULCombine
@@ -14529,7 +14508,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
   case ARMISD::ADDE:    return PerformADDECombine(N, DCI, Subtarget);
   case ARMISD::UMLAL:   return PerformUMLALCombine(N, DCI.DAG, Subtarget);
   case ISD::ADD:        return PerformADDCombine(N, DCI, Subtarget);
-  case ISD::SUB:        return PerformSUBCombine(N, DCI, Subtarget);
+  case ISD::SUB:        return PerformSUBCombine(N, DCI);
   case ISD::MUL:        return PerformMULCombine(N, DCI, Subtarget);
   case ISD::OR:         return PerformORCombine(N, DCI, Subtarget);
   case ISD::XOR:        return PerformXORCombine(N, DCI, Subtarget);
@@ -14887,9 +14866,6 @@ bool ARMTargetLowering::shouldSinkOperands(Instruction *I,
     case Instruction::Mul:
       return true;
     case Instruction::Sub:
-    case Instruction::Shl:
-    case Instruction::LShr:
-    case Instruction::AShr:
       return Operand == 1;
     default:
       return false;

llvm/lib/Target/ARM/ARMInstrMVE.td

@@ -4304,7 +4304,6 @@ defm MVE_VRSHL_qr  : MVE_VxSHL_qr_types<"vrshl",  0b0, 0b1>;
 defm MVE_VQSHL_qr  : MVE_VxSHL_qr_types<"vqshl",  0b1, 0b0>;
 defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
 
-
 let Predicates = [HasMVEInt] in {
   def : Pat<(v4i32 (ARMvshlu (v4i32 MQPR:$Qm), (v4i32 (ARMvdup GPR:$Rm)))),
             (v4i32 (MVE_VSHL_qru32 (v4i32 MQPR:$Qm), GPR:$Rm))>;