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[X86][BMI] Pull out schedule classes from bmi_andn<> and bmi_bls<>
Stop hardwiring classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375470 91177308-0d34-0410-b5e6-96231b3b80d8
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+15
-14
lines changed

2 files changed

+15
-14
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lib/Target/X86/X86InstrArithmetic.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1271,22 +1271,22 @@ let isCompare = 1 in {
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// ANDN Instruction
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//
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multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
1274-
PatFrag ld_frag> {
1274+
PatFrag ld_frag, X86FoldableSchedWrite sched> {
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def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
1278-
Sched<[WriteALU]>;
1278+
Sched<[sched]>;
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def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, EFLAGS,
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(X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
1283-
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
1283+
Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
12851285

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// Complexity is reduced to give and with immediate a chance to match first.
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let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in {
1288-
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1289-
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
1288+
defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V;
1289+
defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, VEX_W;
12901290
}
12911291

12921292
let Predicates = [HasBMI], AddedComplexity = -6 in {

lib/Target/X86/X86InstrInfo.td

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2418,25 +2418,26 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
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}
24192419

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multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2421-
RegisterClass RC, X86MemOperand x86memop> {
2421+
RegisterClass RC, X86MemOperand x86memop,
2422+
X86FoldableSchedWrite sched> {
24222423
let hasSideEffects = 0 in {
24232424
def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
24242425
!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2425-
T8PS, VEX_4V, Sched<[WriteBLS]>;
2426+
T8PS, VEX_4V, Sched<[sched]>;
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let mayLoad = 1 in
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def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2429-
T8PS, VEX_4V, Sched<[WriteBLS.Folded]>;
2430+
T8PS, VEX_4V, Sched<[sched.Folded]>;
24302431
}
24312432
}
24322433

24332434
let Predicates = [HasBMI], Defs = [EFLAGS] in {
2434-
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2435-
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2436-
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2437-
defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2438-
defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2439-
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2435+
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>;
2436+
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W;
2437+
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>;
2438+
defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W;
2439+
defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>;
2440+
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W;
24402441
}
24412442

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//===----------------------------------------------------------------------===//

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