@@ -2418,25 +2418,26 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
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}
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multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
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- RegisterClass RC, X86MemOperand x86memop> {
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+ RegisterClass RC, X86MemOperand x86memop,
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+ X86FoldableSchedWrite sched> {
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let hasSideEffects = 0 in {
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def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
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- T8PS, VEX_4V, Sched<[WriteBLS ]>;
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+ T8PS, VEX_4V, Sched<[sched ]>;
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let mayLoad = 1 in
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def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
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- T8PS, VEX_4V, Sched<[WriteBLS .Folded]>;
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+ T8PS, VEX_4V, Sched<[sched .Folded]>;
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}
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}
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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- defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
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- defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
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- defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
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- defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
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- defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
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- defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
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+ defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS >;
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+ defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS >, VEX_W;
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+ defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS >;
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+ defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS >, VEX_W;
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+ defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS >;
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+ defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS >, VEX_W;
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}
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//===----------------------------------------------------------------------===//
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