Skip to content

Commit 9cbd8cb

Browse files
sparker-armsparker-arm
committed
[ARM][MVE] Add invalidForTailPredication to TSFlags
Set this bit for the MVE reduction instructions to prevent a loop from becoming tail predicated in their presence. Differential Revision: https://reviews.llvm.org/D67444 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372076 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent f6a4020 commit 9cbd8cb

File tree

5 files changed

+197
-0
lines changed

5 files changed

+197
-0
lines changed

‎lib/Target/ARM/ARMInstrFormats.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -408,6 +408,8 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
408408
// mnemonic (when not in an IT block) or preclude it (when in an IT block).
409409
bit thumbArithFlagSetting = 0;
410410

411+
bit invalidForTailPredication = 0;
412+
411413
// If this is a pseudo instruction, mark it isCodeGenOnly.
412414
let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
413415

@@ -419,6 +421,7 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
419421
let TSFlags{14} = canXformTo16Bit;
420422
let TSFlags{18-15} = D.Value;
421423
let TSFlags{19} = thumbArithFlagSetting;
424+
let TSFlags{20} = invalidForTailPredication;
422425

423426
let Constraints = cstr;
424427
let Itinerary = itin;

‎lib/Target/ARM/ARMInstrMVE.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -506,6 +506,7 @@ class MVE_VABAV<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
506506
let Inst{5} = Qm{3};
507507
let Inst{3-1} = Qm{2-0};
508508
let Inst{0} = 0b1;
509+
let invalidForTailPredication = 1;
509510
}
510511

511512
def MVE_VABAVs8 : MVE_VABAV<"s8", 0b0, 0b00>;
@@ -532,6 +533,7 @@ class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
532533
let Inst{5} = A;
533534
let Inst{3-1} = Qm{2-0};
534535
let Inst{0} = 0b0;
536+
let invalidForTailPredication = 1;
535537
}
536538

537539
multiclass MVE_VADDV_A<string suffix, bit U, bits<2> size,
@@ -582,6 +584,7 @@ class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
582584
let Inst{5} = A;
583585
let Inst{3-1} = Qm{2-0};
584586
let Inst{0} = 0b0;
587+
let invalidForTailPredication = 1;
585588
}
586589

587590
multiclass MVE_VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
@@ -619,6 +622,7 @@ class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
619622
let Inst{0} = 0b0;
620623

621624
let Predicates = [HasMVEFloat];
625+
let invalidForTailPredication = 1;
622626
}
623627

624628
multiclass MVE_VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
@@ -655,6 +659,7 @@ class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
655659
let Inst{6-5} = 0b00;
656660
let Inst{3-1} = Qm{2-0};
657661
let Inst{0} = 0b0;
662+
let invalidForTailPredication = 1;
658663
}
659664

660665
multiclass MVE_VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
@@ -727,6 +732,7 @@ class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
727732
let Inst{5} = A;
728733
let Inst{3-1} = Qm{2-0};
729734
let Inst{0} = bit_0;
735+
let invalidForTailPredication = 1;
730736
}
731737

732738
multiclass MVE_VMLAMLSDAV_A<string iname, string x, string suffix,
@@ -802,6 +808,7 @@ class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
802808
let Inst{5} = A;
803809
let Inst{3-1} = Qm{2-0};
804810
let Inst{0} = bit_0;
811+
let invalidForTailPredication = 1;
805812
}
806813

807814
multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,

‎lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,10 @@ namespace ARMII {
393393
// in an IT block).
394394
ThumbArithFlagSetting = 1 << 19,
395395

396+
// Whether an instruction should be excluded from an MVE tail-predicated
397+
// loop.
398+
InvalidForTailPredication = 1 << 20,
399+
396400
//===------------------------------------------------------------------===//
397401
// Code ___domain.
398402
DomainShift = 15,

‎unittests/Target/ARM/CMakeLists.txt

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
include_directories(
2+
${CMAKE_SOURCE_DIR}/lib/Target/ARM
3+
${CMAKE_BINARY_DIR}/lib/Target/ARM
4+
)
5+
6+
set(LLVM_LINK_COMPONENTS
7+
ARMCodeGen
8+
ARMDesc
9+
ARMInfo
10+
MC
11+
Support
12+
Target
13+
)
14+
15+
add_llvm_unittest(ARMTests
16+
MachineInstrTest.cpp
17+
)

‎unittests/Target/ARM/MachineInstrTest.cpp

Lines changed: 166 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,166 @@
1+
#include "ARMBaseInstrInfo.h"
2+
#include "ARMSubtarget.h"
3+
#include "ARMTargetMachine.h"
4+
#include "llvm/Support/TargetRegistry.h"
5+
#include "llvm/Support/TargetSelect.h"
6+
#include "llvm/Target/TargetMachine.h"
7+
#include "llvm/Target/TargetOptions.h"
8+
9+
#include "gtest/gtest.h"
10+
11+
using namespace llvm;
12+
13+
// Test for instructions that aren't immediately obviously valid within a
14+
// tail-predicated loop. This should be marked up in their tablegen
15+
// descriptions. Currently the horizontal vector operations are tagged.
16+
// TODO Add instructions that perform:
17+
// - truncation,
18+
// - extensions,
19+
// - byte swapping,
20+
// - others?
21+
TEST(MachineInstrInvalidTailPredication, IsCorrect) {
22+
LLVMInitializeARMTargetInfo();
23+
LLVMInitializeARMTarget();
24+
LLVMInitializeARMTargetMC();
25+
26+
auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
27+
std::string Error;
28+
const Target *T = TargetRegistry::lookupTarget(TT, Error);
29+
if (!T) {
30+
dbgs() << Error;
31+
return;
32+
}
33+
34+
TargetOptions Options;
35+
auto TM = std::unique_ptr<LLVMTargetMachine>(
36+
static_cast<LLVMTargetMachine*>(
37+
T->createTargetMachine(TT, "generic", "", Options, None, None,
38+
CodeGenOpt::Default)));
39+
auto MII = TM->getMCInstrInfo();
40+
41+
using namespace ARM;
42+
43+
auto IsInvalidTPOpcode = [](unsigned Opcode) {
44+
switch (Opcode) {
45+
case MVE_VABAVs8:
46+
case MVE_VABAVs16:
47+
case MVE_VABAVs32:
48+
case MVE_VABAVu8:
49+
case MVE_VABAVu16:
50+
case MVE_VABAVu32:
51+
case MVE_VADDVs8acc:
52+
case MVE_VADDVs16acc:
53+
case MVE_VADDVs32acc:
54+
case MVE_VADDVu8acc:
55+
case MVE_VADDVu16acc:
56+
case MVE_VADDVu32acc:
57+
case MVE_VADDVs8no_acc:
58+
case MVE_VADDVs16no_acc:
59+
case MVE_VADDVs32no_acc:
60+
case MVE_VADDVu8no_acc:
61+
case MVE_VADDVu16no_acc:
62+
case MVE_VADDVu32no_acc:
63+
case MVE_VADDLVs32no_acc:
64+
case MVE_VADDLVu32no_acc:
65+
case MVE_VADDLVs32acc:
66+
case MVE_VADDLVu32acc:
67+
case MVE_VMLADAVas16:
68+
case MVE_VMLADAVas32:
69+
case MVE_VMLADAVas8:
70+
case MVE_VMLADAVau16:
71+
case MVE_VMLADAVau32:
72+
case MVE_VMLADAVau8:
73+
case MVE_VMLADAVaxs16:
74+
case MVE_VMLADAVaxs32:
75+
case MVE_VMLADAVaxs8:
76+
case MVE_VMLADAVs16:
77+
case MVE_VMLADAVs32:
78+
case MVE_VMLADAVs8:
79+
case MVE_VMLADAVu16:
80+
case MVE_VMLADAVu32:
81+
case MVE_VMLADAVu8:
82+
case MVE_VMLADAVxs16:
83+
case MVE_VMLADAVxs32:
84+
case MVE_VMLADAVxs8:
85+
case MVE_VMLALDAVas16:
86+
case MVE_VMLALDAVas32:
87+
case MVE_VMLALDAVau16:
88+
case MVE_VMLALDAVau32:
89+
case MVE_VMLALDAVaxs16:
90+
case MVE_VMLALDAVaxs32:
91+
case MVE_VMLALDAVs16:
92+
case MVE_VMLALDAVs32:
93+
case MVE_VMLALDAVu16:
94+
case MVE_VMLALDAVu32:
95+
case MVE_VMLALDAVxs16:
96+
case MVE_VMLALDAVxs32:
97+
case MVE_VMLSDAVas16:
98+
case MVE_VMLSDAVas32:
99+
case MVE_VMLSDAVas8:
100+
case MVE_VMLSDAVaxs16:
101+
case MVE_VMLSDAVaxs32:
102+
case MVE_VMLSDAVaxs8:
103+
case MVE_VMLSDAVs16:
104+
case MVE_VMLSDAVs32:
105+
case MVE_VMLSDAVs8:
106+
case MVE_VMLSDAVxs16:
107+
case MVE_VMLSDAVxs32:
108+
case MVE_VMLSDAVxs8:
109+
case MVE_VMLSLDAVas16:
110+
case MVE_VMLSLDAVas32:
111+
case MVE_VMLSLDAVaxs16:
112+
case MVE_VMLSLDAVaxs32:
113+
case MVE_VMLSLDAVs16:
114+
case MVE_VMLSLDAVs32:
115+
case MVE_VMLSLDAVxs16:
116+
case MVE_VMLSLDAVxs32:
117+
case MVE_VRMLALDAVHas32:
118+
case MVE_VRMLALDAVHau32:
119+
case MVE_VRMLALDAVHaxs32:
120+
case MVE_VRMLALDAVHs32:
121+
case MVE_VRMLALDAVHu32:
122+
case MVE_VRMLALDAVHxs32:
123+
case MVE_VRMLSLDAVHas32:
124+
case MVE_VRMLSLDAVHaxs32:
125+
case MVE_VRMLSLDAVHs32:
126+
case MVE_VRMLSLDAVHxs32:
127+
case MVE_VMAXNMVf16:
128+
case MVE_VMINNMVf16:
129+
case MVE_VMAXNMVf32:
130+
case MVE_VMINNMVf32:
131+
case MVE_VMAXNMAVf16:
132+
case MVE_VMINNMAVf16:
133+
case MVE_VMAXNMAVf32:
134+
case MVE_VMINNMAVf32:
135+
case MVE_VMAXVs8:
136+
case MVE_VMAXVs16:
137+
case MVE_VMAXVs32:
138+
case MVE_VMAXVu8:
139+
case MVE_VMAXVu16:
140+
case MVE_VMAXVu32:
141+
case MVE_VMINVs8:
142+
case MVE_VMINVs16:
143+
case MVE_VMINVs32:
144+
case MVE_VMINVu8:
145+
case MVE_VMINVu16:
146+
case MVE_VMINVu32:
147+
case MVE_VMAXAVs8:
148+
case MVE_VMAXAVs16:
149+
case MVE_VMAXAVs32:
150+
case MVE_VMINAVs8:
151+
case MVE_VMINAVs16:
152+
case MVE_VMINAVs32:
153+
return true;
154+
default:
155+
return false;
156+
}
157+
};
158+
159+
for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
160+
uint64_t Flags = MII->get(i).TSFlags;
161+
bool Invalid = (Flags & ARMII::InvalidForTailPredication) != 0;
162+
ASSERT_EQ(IsInvalidTPOpcode(i), Invalid)
163+
<< MII->getName(i)
164+
<< ": mismatched expectation for tail-predicated safety\n";
165+
}
166+
}

0 commit comments

Comments
 (0)