[SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349186 91177308-0d34-0410-b5e6-96231b3b80d8

Author: Krzysztof Parzyszek

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

@@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
   unsigned NumOps = Node->getNumOperands();
+  // REG_SEQUENCE can "inherit" a chain from a subnode.
+  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
+    --NumOps; // Ignore chain if it exists.
+
   assert((NumOps & 1) == 1 &&
          "REG_SEQUENCE must have an odd number of operands!");
   for (unsigned i = 1; i != NumOps; ++i) {