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[NFC][RA] Refactor RABasic into a Separate Header (llvm#149555)
This change refactors the RABasic type by moving it from RegAllocBasic.cpp to a new header file, RegAllocBasic.h. This separation of header and implementation aligns with the structure used by other register allocators, such as RegAllocGreedy. The refactoring is intended to facilitate future use of RABasic in other contexts.
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‎llvm/lib/CodeGen/RegAllocBasic.cpp

Lines changed: 6 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -5,35 +5,31 @@
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RABasic function pass, which provides a minimal
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// implementation of the basic register allocator.
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//
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///
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/// \file
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/// This file defines the RABasic function pass, which provides a minimal
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/// implementation of the basic register allocator.
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///
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//===----------------------------------------------------------------------===//
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#include "RegAllocBasic.h"
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#include "AllocationOrder.h"
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#include "RegAllocBase.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ProfileSummaryInfo.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveDebugVariables.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/Spiller.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <queue>
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using namespace llvm;
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@@ -42,89 +38,8 @@ using namespace llvm;
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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createBasicRegisterAllocator);
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namespace {
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struct CompSpillWeight {
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bool operator()(const LiveInterval *A, const LiveInterval *B) const {
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return A->weight() < B->weight();
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}
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};
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}
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namespace {
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass,
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public RegAllocBase,
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private LiveRangeEdit::Delegate {
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// context
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MachineFunction *MF = nullptr;
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// state
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std::unique_ptr<Spiller> SpillerInstance;
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std::priority_queue<const LiveInterval *, std::vector<const LiveInterval *>,
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CompSpillWeight>
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Queue;
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// Scratch space. Allocated here to avoid repeated malloc calls in
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// selectOrSplit().
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BitVector UsableRegs;
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bool LRE_CanEraseVirtReg(Register) override;
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void LRE_WillShrinkVirtReg(Register) override;
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public:
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RABasic(const RegAllocFilterFunc F = nullptr);
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/// Return the pass name.
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StringRef getPassName() const override { return "Basic Register Allocator"; }
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/// RABasic analysis usage.
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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void releaseMemory() override;
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Spiller &spiller() override { return *SpillerInstance; }
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void enqueueImpl(const LiveInterval *LI) override { Queue.push(LI); }
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const LiveInterval *dequeue() override {
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if (Queue.empty())
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return nullptr;
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const LiveInterval *LI = Queue.top();
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Queue.pop();
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return LI;
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}
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MCRegister selectOrSplit(const LiveInterval &VirtReg,
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SmallVectorImpl<Register> &SplitVRegs) override;
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/// Perform register allocation.
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bool runOnMachineFunction(MachineFunction &mf) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().setNoPHIs();
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}
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MachineFunctionProperties getClearedProperties() const override {
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return MachineFunctionProperties().setIsSSA();
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}
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// Helper for spilling all live virtual registers currently unified under preg
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// that interfere with the most recently queried lvr. Return true if spilling
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// was successful, and append any new spilled/split intervals to splitLVRs.
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bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
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SmallVectorImpl<Register> &SplitVRegs);
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static char ID;
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};
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char RABasic::ID = 0;
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} // end anonymous namespace
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char &llvm::RABasicID = RABasic::ID;
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INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",

‎llvm/lib/CodeGen/RegAllocBasic.h

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
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//===-- RegAllocBasic.h - Basic Register Allocator Header -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file declares the RABasic class, which provides a minimal
11+
/// implementation of the basic register allocator.
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///
13+
//===----------------------------------------------------------------------===//
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15+
#ifndef LLVM_CODEGEN_REGALLOCBASIC_H
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#define LLVM_CODEGEN_REGALLOCBASIC_H
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#include "RegAllocBase.h"
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#include "llvm/CodeGen/LiveRangeEdit.h"
20+
#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/Spiller.h"
22+
#include <queue>
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namespace llvm {
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struct CompSpillWeight {
27+
bool operator()(const LiveInterval *A, const LiveInterval *B) const {
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return A->weight() < B->weight();
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}
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};
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/// RABasic provides a minimal implementation of the basic register allocation
33+
/// algorithm. It prioritizes live virtual registers by spill weight and spills
34+
/// whenever a register is unavailable. This is not practical in production but
35+
/// provides a useful baseline both for measuring other allocators and comparing
36+
/// the speed of the basic algorithm against other styles of allocators.
37+
class LLVM_LIBRARY_VISIBILITY RABasic : public MachineFunctionPass,
38+
public RegAllocBase,
39+
private LiveRangeEdit::Delegate {
40+
// context
41+
MachineFunction *MF = nullptr;
42+
43+
// state
44+
std::unique_ptr<Spiller> SpillerInstance;
45+
std::priority_queue<const LiveInterval *, std::vector<const LiveInterval *>,
46+
CompSpillWeight>
47+
Queue;
48+
49+
// Scratch space. Allocated here to avoid repeated malloc calls in
50+
// selectOrSplit().
51+
BitVector UsableRegs;
52+
53+
bool LRE_CanEraseVirtReg(Register) override;
54+
void LRE_WillShrinkVirtReg(Register) override;
55+
56+
public:
57+
RABasic(const RegAllocFilterFunc F = nullptr);
58+
59+
/// Return the pass name.
60+
StringRef getPassName() const override { return "Basic Register Allocator"; }
61+
62+
/// RABasic analysis usage.
63+
void getAnalysisUsage(AnalysisUsage &AU) const override;
64+
65+
void releaseMemory() override;
66+
67+
Spiller &spiller() override { return *SpillerInstance; }
68+
69+
void enqueueImpl(const LiveInterval *LI) override { Queue.push(LI); }
70+
71+
const LiveInterval *dequeue() override {
72+
if (Queue.empty())
73+
return nullptr;
74+
const LiveInterval *LI = Queue.top();
75+
Queue.pop();
76+
return LI;
77+
}
78+
79+
MCRegister selectOrSplit(const LiveInterval &VirtReg,
80+
SmallVectorImpl<Register> &SplitVRegs) override;
81+
82+
/// Perform register allocation.
83+
bool runOnMachineFunction(MachineFunction &mf) override;
84+
85+
MachineFunctionProperties getRequiredProperties() const override {
86+
return MachineFunctionProperties().set(
87+
MachineFunctionProperties::Property::NoPHIs);
88+
}
89+
90+
MachineFunctionProperties getClearedProperties() const override {
91+
return MachineFunctionProperties().set(
92+
MachineFunctionProperties::Property::IsSSA);
93+
}
94+
95+
// Helper for spilling all live virtual registers currently unified under preg
96+
// that interfere with the most recently queried lvr. Return true if spilling
97+
// was successful, and append any new spilled/split intervals to splitLVRs.
98+
bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
99+
SmallVectorImpl<Register> &SplitVRegs);
100+
101+
static char ID;
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};
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} // namespace llvm
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#endif

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