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[CodeGen] MachineVerifier to check early-clobber constraint #151421

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[CodeGen] MachineVerifier to check early-clobber constraint #151421

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[CodeGen] MachineVerifier to check early-clobber constraint
AbhayKanhere Jul 30, 2025
f70f3ba
Fix the test failure with this PR, update AMDGPU code that did not se…
AbhayKanhere Aug 4, 2025
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7 changes: 7 additions & 0 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2325,6 +2325,13 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
report("Missing mayStore flag", MI);
}

// Verify earlyClobber def operand
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
if (!MI->getOperand(0).isReg())
report("Early clobber must be a register", MI);
if (!MI->getOperand(0).isEarlyClobber())
report("Missing earlyClobber flag", MI);
}
// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
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14 changes: 12 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -116,8 +116,13 @@ bool AMDGPUInstructionSelector::constrainCopyLikeIntrin(MachineInstr &MI,
if (!DstRC || DstRC != SrcRC)
return false;

return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
auto result = RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI);
const MCInstrDesc &MCID = MI.getDesc();
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
MI.getOperand(0).setIsEarlyClobber(true);
}
return result;
}

bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
Expand Down Expand Up @@ -593,6 +598,7 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
I.setDesc(TII.get(Opc));
I.addOperand(*MF, MachineOperand::CreateImm(0));
I.addImplicitDefUseOperands(*MF);
I.getOperand(0).setIsEarlyClobber(true);
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This should be a property of the instruction definition and not require manual setting

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@AbhayKanhere AbhayKanhere Aug 5, 2025 •
edited
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earlyClobber and TiedTo are two of the OperandConstraint -- we check for tiedTo but not earlyClobber in machine verifier. on CPU targets register allocators strictly look at earlyClobber on operand. Recently we discovered that when MI.setDesc is used to modify the opcode, this constraint on Operand is not updated. However if new instruction is built and operand added using addOperand() , then earlyClobber is set correctly.. Looks like AMDGPU backend makes heavy use of setDesc (since the earlySelect expects in-place change to opcode) but does not update earlyClobber. I found many instances of this.

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@AbhayKanhere AbhayKanhere Aug 5, 2025 •
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Internally we discussed a variant for MI.setDesc(MCID, bool updateOpConstraint=false) that updates OperandConstraints if passed true, but setDesc is often part of a set of update operations on operands and not the last in the sequence so it is not always possible to update operand constraints there.

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The problem here is that MI.setDesc which only updates opcode, and MI.addOperand following MI.buildInstr/ that create new instruction behave differently in how Operand constraints are updated.

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ok, still needs tests

return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}

Expand Down Expand Up @@ -3795,6 +3801,10 @@ bool AMDGPUInstructionSelector::selectSMFMACIntrin(MachineInstr &MI) const {
MI.removeOperand(1); // Intrinsic ID
MI.addOperand(VDst_In); // Readd VDst_In to the end
MI.addImplicitDefUseOperands(*MI.getParent()->getParent());
const MCInstrDesc &MCID = MI.getDesc();
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
MI.getOperand(0).setIsEarlyClobber(true);
}
return true;
}

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4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Expand Up @@ -687,6 +687,10 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
if (!TII->isOperandLegal(*MI, OpNo, &New))
return false;

const MCInstrDesc &MCID = MI->getDesc();
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
MI->getOperand(0).setIsEarlyClobber(true);
}
Old.ChangeToImmediate(*ImmVal);
return true;
}
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
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Expand Up @@ -27,11 +27,11 @@ define amdgpu_kernel void @set_inactive_imm_poison(ptr addrspace(1) %out) {
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: v_mov_b32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, v0
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: buffer_store_dword v1, off, s[0:3], 0
; GCN-NEXT: s_endpgm
%tmp.0 = call i32 @llvm.amdgcn.set.inactive.i32(i32 1, i32 poison) #0
%tmp = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp.0)
Expand Down Expand Up @@ -68,12 +68,12 @@ define amdgpu_kernel void @set_inactive_imm_poison_64(ptr addrspace(1) %out) {
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_mov_b32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, v1
; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: buffer_store_dwordx2 v[2:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
%tmp.0 = call i64 @llvm.amdgcn.set.inactive.i64(i64 1, i64 poison) #0
%tmp = call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp.0)
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
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Expand Up @@ -165,10 +165,10 @@ define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr a
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[6:7]
; GFX10-NEXT: global_load_dword v2, v0, s[2:3]
; GFX10-NEXT: global_load_dword v3, v0, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v1, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s2, v2, v3, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm
Expand All @@ -179,15 +179,15 @@ define amdgpu_kernel void @v_mul_i64_zext_src0_src1(ptr addrspace(1) %out, ptr a
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-NEXT: global_load_b32 v0, v0, s[4:5]
; GFX11-NEXT: global_load_b32 v2, v0, s[2:3]
; GFX11-NEXT: global_load_b32 v3, v0, s[4:5]
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v1, v0, 0
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, v3, 0
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
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