Skip to content

[CodeGen] MachineVerifier to check early-clobber constraint #151421

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions llvm/lib/CodeGen/MachineVerifier.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2325,6 +2325,13 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
report("Missing mayStore flag", MI);
}

// Verify earlyClobber def operand
if (MCID.getOperandConstraint(0, MCOI::EARLY_CLOBBER) != -1) {
if (!MI->getOperand(0).isReg())
report("Early clobber must be a register", MI);
if (!MI->getOperand(0).isEarlyClobber())
report("Missing earlyClobber flag", MI);
}
// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -584,6 +584,7 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
I.setDesc(TII.get(Opc));
I.addOperand(*MF, MachineOperand::CreateImm(0));
I.addImplicitDefUseOperands(*MF);
I.getOperand(0).setIsEarlyClobber(true);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This should be a property of the instruction definition and not require manual setting

Copy link
Contributor Author

@AbhayKanhere AbhayKanhere Aug 5, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

earlyClobber and TiedTo are two of the OperandConstraint -- we check for tiedTo but not earlyClobber in machine verifier. on CPU targets register allocators strictly look at earlyClobber on operand. Recently we discovered that when MI.setDesc is used to modify the opcode, this constraint on Operand is not updated. However if new instruction is built and operand added using addOperand() , then earlyClobber is set correctly.. Looks like AMDGPU backend makes heavy use of setDesc (since the earlySelect expects in-place change to opcode) but does not update earlyClobber. I found many instances of this.

Copy link
Contributor Author

@AbhayKanhere AbhayKanhere Aug 5, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Internally we discussed a variant for MI.setDesc(MCID, bool updateOpConstraint=false) that updates OperandConstraints if passed true, but setDesc is often part of a set of update operations on operands and not the last in the sequence so it is not always possible to update operand constraints there.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The problem here is that MI.setDesc which only updates opcode, and MI.addOperand following MI.buildInstr/ that create new instruction behave differently in how Operand constraints are updated.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ok, still needs tests

return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}

Expand Down
Loading