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[AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes #151256

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Jul 30, 2025
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[AMDGPU] gfx1250 V_{MIN|MAX}_{I|U}64 opcodes #151256

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31 changes: 24 additions & 7 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1342,13 +1342,30 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0);

if (ST.hasVOP3PInsts()) {
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS})
.legalFor({S32, S16, V2S16})
.clampMaxNumElements(0, S16, 2)
.minScalar(0, S16)
.widenScalarToNextPow2(0)
.scalarize(0)
.lower();
getActionDefinitionsBuilder(G_ABS)
.legalFor({S32, S16, V2S16})
.clampMaxNumElements(0, S16, 2)
.minScalar(0, S16)
.widenScalarToNextPow2(0)
.scalarize(0)
.lower();
if (ST.hasIntMinMax64()) {
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
.legalFor({S32, S16, S64, V2S16})
.clampMaxNumElements(0, S16, 2)
.minScalar(0, S16)
.widenScalarToNextPow2(0)
.scalarize(0)
.lower();
} else {
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
.legalFor({S32, S16, V2S16})
.clampMaxNumElements(0, S16, 2)
.minScalar(0, S16)
.widenScalarToNextPow2(0)
.scalarize(0)
.lower();
}
} else {
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX, G_ABS})
.legalFor({S32, S16})
Expand Down
16 changes: 12 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Expand Up @@ -4009,10 +4009,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_SADDE:
case AMDGPU::G_USUBE:
case AMDGPU::G_SSUBE:
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX:
case AMDGPU::G_ABS:
case AMDGPU::G_SHUFFLE_VECTOR:
case AMDGPU::G_SBFX:
Expand All @@ -4022,6 +4018,18 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (isSALUMapping(MI))
return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI);
case AMDGPU::G_SMIN:
case AMDGPU::G_SMAX:
case AMDGPU::G_UMIN:
case AMDGPU::G_UMAX:
if (isSALUMapping(MI)) {
// There are no scalar 64-bit min and max, use vector instruction instead.
if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 64 &&
Subtarget.hasIntMinMax64())
return getDefaultMappingVOP(MI);
return getDefaultMappingSOP(MI);
}
return getDefaultMappingVOP(MI);
case AMDGPU::G_FADD:
case AMDGPU::G_FSUB:
case AMDGPU::G_FMUL:
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/GCNSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1532,6 +1532,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// instructions.
bool hasMadU64U32NoCarry() const { return GFX1250Insts; }

// \returns true if the target has V_{MIN|MAX}_{I|U}64 instructions.
bool hasIntMinMax64() const { return GFX1250Insts; }

// \returns true if the target has V_PK_ADD_{MIN|MAX}_{I|U}16 instructions.
bool hasPkAddMinMaxInsts() const { return GFX1250Insts; }

Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -909,6 +909,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Custom);
}

if (Subtarget->hasIntMinMax64())
setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i64,
Legal);

setOperationAction(ISD::INTRINSIC_WO_CHAIN,
{MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16,
MVT::bf16, MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::i128,
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -202,6 +202,13 @@ defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, f
} // End SchedRW = [WriteDoubleAdd]
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0, AddedComplexity = 1

let SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd] in {
defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_DPP, smax>;
defm V_MAX_U64 : VOP3Inst <"v_max_u64", VOP_I64_I64_I64_DPP, umax>;
defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_DPP, smin>;
defm V_MIN_U64 : VOP3Inst <"v_min_u64", VOP_I64_I64_I64_DPP, umin>;
} // End SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd]

} // End isReMaterializable = 1

let Uses = [MODE, VCC, EXEC] in {
Expand Down Expand Up @@ -1810,6 +1817,10 @@ defm V_BITOP3_B32 : VOP3_Real_BITOP3_gfx1250<0x234>;
defm V_MAD_U32 : VOP3Only_Realtriple_gfx1250<0x235>;
defm V_MAD_NC_U64_U32 : VOP3Only_Realtriple_gfx1250<0x2fa>;
defm V_MAD_NC_I64_I32 : VOP3Only_Realtriple_gfx1250<0x2fb>;
defm V_MIN_U64 : VOP3Only_Realtriple_gfx1250<0x318>;
defm V_MAX_U64 : VOP3Only_Realtriple_gfx1250<0x319>;
defm V_MIN_I64 : VOP3Only_Realtriple_gfx1250<0x31a>;
defm V_MAX_I64 : VOP3Only_Realtriple_gfx1250<0x31b>;

defm V_CVT_PK_FP8_F32 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x369, "v_cvt_pk_fp8_f32">;
defm V_CVT_PK_BF8_F32 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x36a, "v_cvt_pk_bf8_f32">;
Expand Down
192 changes: 192 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs-i64.ll
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@@ -0,0 +1,192 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1250 < %s | FileCheck %s

declare i64 @llvm.umin.i64(i64, i64)
declare i64 @llvm.umax.i64(i64, i64)
declare i64 @llvm.smin.i64(i64, i64)
declare i64 @llvm.smax.i64(i64, i64)
declare i64 @llvm.abs.i64(i64, i1)

declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)
declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)
declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)

define i64 @test_umin_i64(i64 %a, i64 %b) {
; CHECK-LABEL: test_umin_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[2:3]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.umin.i64(i64 %a, i64 %b)
ret i64 %r
}

define i64 @test_umax_i64(i64 %a, i64 %b) {
; CHECK-LABEL: test_umax_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[2:3]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.umax.i64(i64 %a, i64 %b)
ret i64 %r
}

define i64 @test_smin_i64(i64 %a, i64 %b) {
; CHECK-LABEL: test_smin_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[2:3]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.smin.i64(i64 %a, i64 %b)
ret i64 %r
}

define i64 @test_smax_i64(i64 %a, i64 %b) {
; CHECK-LABEL: test_smax_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[2:3]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.smax.i64(i64 %a, i64 %b)
ret i64 %r
}

define <4 x i64> @test_umin_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: test_umin_v4i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_min_u64 v[0:1], v[0:1], v[8:9]
; CHECK-NEXT: v_min_u64 v[2:3], v[2:3], v[10:11]
; CHECK-NEXT: v_min_u64 v[4:5], v[4:5], v[12:13]
; CHECK-NEXT: v_min_u64 v[6:7], v[6:7], v[14:15]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
}

define <4 x i64> @test_umax_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: test_umax_v4i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_max_u64 v[0:1], v[0:1], v[8:9]
; CHECK-NEXT: v_max_u64 v[2:3], v[2:3], v[10:11]
; CHECK-NEXT: v_max_u64 v[4:5], v[4:5], v[12:13]
; CHECK-NEXT: v_max_u64 v[6:7], v[6:7], v[14:15]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
}

define <4 x i64> @test_smin_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: test_smin_v4i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_min_i64 v[0:1], v[0:1], v[8:9]
; CHECK-NEXT: v_min_i64 v[2:3], v[2:3], v[10:11]
; CHECK-NEXT: v_min_i64 v[4:5], v[4:5], v[12:13]
; CHECK-NEXT: v_min_i64 v[6:7], v[6:7], v[14:15]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
}

define <4 x i64> @test_smax_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: test_smax_v4i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_max_i64 v[0:1], v[0:1], v[8:9]
; CHECK-NEXT: v_max_i64 v[2:3], v[2:3], v[10:11]
; CHECK-NEXT: v_max_i64 v[4:5], v[4:5], v[12:13]
; CHECK-NEXT: v_max_i64 v[6:7], v[6:7], v[14:15]
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %r
}

define i64 @test_abs_i64(i64 %a) {
; CHECK-LABEL: test_abs_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; CHECK-NEXT: v_mov_b32_e32 v3, v2
; CHECK-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2
; CHECK-NEXT: s_set_pc_i64 s[30:31]
%r = call i64 @llvm.abs.i64(i64 %a, i1 0)
ret i64 %r
}

define amdgpu_ps i64 @test_umin_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_umin_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_min_u64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: v_readfirstlane_b32 s1, v1
; CHECK-NEXT: ; return to shader part epilog
%r = call i64 @llvm.umin.i64(i64 %a, i64 %b)
ret i64 %r
}

define amdgpu_ps i64 @test_umax_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_umax_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_max_u64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: v_readfirstlane_b32 s1, v1
; CHECK-NEXT: ; return to shader part epilog
%r = call i64 @llvm.umax.i64(i64 %a, i64 %b)
ret i64 %r
}

define amdgpu_ps i64 @test_smin_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_smin_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_min_i64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: v_readfirstlane_b32 s1, v1
; CHECK-NEXT: ; return to shader part epilog
%r = call i64 @llvm.smin.i64(i64 %a, i64 %b)
ret i64 %r
}

define amdgpu_ps i64 @test_smax_i64_s(i64 inreg %a, i64 inreg %b) {
; CHECK-LABEL: test_smax_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: v_max_i64 v[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: v_readfirstlane_b32 s1, v1
; CHECK-NEXT: ; return to shader part epilog
%r = call i64 @llvm.smax.i64(i64 %a, i64 %b)
ret i64 %r
}

define amdgpu_ps i64 @test_abs_i64_s(i64 inreg %a) {
; CHECK-LABEL: test_abs_i64_s:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_ashr_i32 s2, s1, 31
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; CHECK-NEXT: s_mov_b32 s3, s2
; CHECK-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; CHECK-NEXT: ; return to shader part epilog
%r = call i64 @llvm.abs.i64(i64 %a, i1 0)
ret i64 %r
}
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