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[X86][APX] Do optimizeMemoryInst for v1X masked load/store #151331

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Merged
merged 3 commits into from
Jul 31, 2025
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[X86][APX] Do optimizeMemoryInst for v1X masked load/store #151331

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bf50bed
[X86][APX] Do optimizeMemoryInst for v1X masked load/store
phoebewang Jul 30, 2025
f51c6bd
Add load
phoebewang Jul 31, 2025
a9cb823
Merge branch 'main' into APX
phoebewang Jul 31, 2025
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23 changes: 23 additions & 0 deletions llvm/lib/CodeGen/CodeGenPrepare.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2769,6 +2769,29 @@ bool CodeGenPrepare::optimizeCallInst(CallInst *CI, ModifyDT &ModifiedDT) {
return optimizeGatherScatterInst(II, II->getArgOperand(0));
case Intrinsic::masked_scatter:
return optimizeGatherScatterInst(II, II->getArgOperand(1));
case Intrinsic::masked_load:
// Treat v1X masked load as load X type.
if (auto *VT = dyn_cast<FixedVectorType>(II->getType())) {
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Add a test for load too?

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We have one in llvm/test/CodeGen/X86/isel-sink.ll: https://godbolt.org/z/5zhjr4ses

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I misunderstood your point. Added in f51c6bd

if (VT->getNumElements() == 1) {
Value *PtrVal = II->getArgOperand(0);
unsigned AS = PtrVal->getType()->getPointerAddressSpace();
if (optimizeMemoryInst(II, PtrVal, VT->getElementType(), AS))
return true;
}
}
return false;
case Intrinsic::masked_store:
// Treat v1X masked store as store X type.
if (auto *VT =
dyn_cast<FixedVectorType>(II->getArgOperand(0)->getType())) {
if (VT->getNumElements() == 1) {
Value *PtrVal = II->getArgOperand(1);
unsigned AS = PtrVal->getType()->getPointerAddressSpace();
if (optimizeMemoryInst(II, PtrVal, VT->getElementType(), AS))
return true;
}
}
return false;
}

SmallVector<Value *, 2> PtrOps;
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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/X86/apx/cf.ll
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Expand Up @@ -194,3 +194,24 @@ entry:
call void @llvm.masked.store.v1i64.p0(<1 x i64> %3, ptr %p, i32 4, <1 x i1> %0)
ret void
}

define void @sink_gep(ptr %p, i1 %cond) {
; CHECK-LABEL: sink_gep:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb $1, %sil
; CHECK-NEXT: cfcmovnel %eax, 112(%rdi)
; CHECK-NEXT: cfcmovnel 112(%rdi), %eax
; CHECK-NEXT: movl %eax, (%rdi)
; CHECK-NEXT: retq
entry:
%0 = getelementptr i8, ptr %p, i64 112
br label %next

next:
%1 = bitcast i1 %cond to <1 x i1>
call void @llvm.masked.store.v1i32.p0(<1 x i32> zeroinitializer, ptr %0, i32 1, <1 x i1> %1)
%2 = call <1 x i32> @llvm.masked.load.v1i32.p0(ptr %0, i32 1, <1 x i1> %1, <1 x i32> zeroinitializer)
store <1 x i32> %2, ptr %p, align 4
ret void
}