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[NVPTX] Cleanup various vestigial elements and fold together more table-gen (NFC) #151447

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Merged
merged 2 commits into from
Jul 31, 2025
Merged

[NVPTX] Cleanup various vestigial elements and fold together more table-gen (NFC) #151447

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ad50704
nfc cleanup
AlexMaclean Jul 31, 2025
c08caf3
nfc cleanup 2
AlexMaclean Jul 31, 2025
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10 changes: 0 additions & 10 deletions llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -391,16 +391,6 @@ void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
}
}

void NVPTXInstPrinter::printOffseti32imm(const MCInst *MI, int OpNum,
raw_ostream &O) {
auto &Op = MI->getOperand(OpNum);
assert(Op.isImm() && "Invalid operand");
if (Op.getImm() != 0) {
O << "+";
printOperand(MI, OpNum, O);
}
}

void NVPTXInstPrinter::printHexu32imm(const MCInst *MI, int OpNum,
raw_ostream &O) {
int64_t Imm = MI->getOperand(OpNum).getImm();
Expand Down
1 change: 0 additions & 1 deletion llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,6 @@ class NVPTXInstPrinter : public MCInstPrinter {
StringRef Modifier = {});
void printMemOperand(const MCInst *MI, int OpNum, raw_ostream &O,
StringRef Modifier = {});
void printOffseti32imm(const MCInst *MI, int OpNum, raw_ostream &O);
void printHexu32imm(const MCInst *MI, int OpNum, raw_ostream &O);
void printProtoIdent(const MCInst *MI, int OpNum, raw_ostream &O);
void printPrmtMode(const MCInst *MI, int OpNum, raw_ostream &O);
Expand Down
5 changes: 1 addition & 4 deletions llvm/lib/Target/NVPTX/NVPTXForwardParams.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -56,15 +56,12 @@ static bool traverseMoveUse(MachineInstr &U, const MachineRegisterInfo &MRI,
case NVPTX::LD_i16:
case NVPTX::LD_i32:
case NVPTX::LD_i64:
case NVPTX::LD_i8:
case NVPTX::LDV_i16_v2:
case NVPTX::LDV_i16_v4:
case NVPTX::LDV_i32_v2:
case NVPTX::LDV_i32_v4:
case NVPTX::LDV_i64_v2:
case NVPTX::LDV_i64_v4:
case NVPTX::LDV_i8_v2:
case NVPTX::LDV_i8_v4: {
case NVPTX::LDV_i64_v4: {
LoadInsts.push_back(&U);
return true;
}
Expand Down
85 changes: 38 additions & 47 deletions llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1003,14 +1003,10 @@ void NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
// Helper function template to reduce amount of boilerplate code for
// opcode selection.
static std::optional<unsigned>
pickOpcodeForVT(MVT::SimpleValueType VT, std::optional<unsigned> Opcode_i8,
std::optional<unsigned> Opcode_i16,
pickOpcodeForVT(MVT::SimpleValueType VT, std::optional<unsigned> Opcode_i16,
std::optional<unsigned> Opcode_i32,
std::optional<unsigned> Opcode_i64) {
switch (VT) {
case MVT::i1:
case MVT::i8:
return Opcode_i8;
case MVT::f16:
case MVT::i16:
case MVT::bf16:
Expand Down Expand Up @@ -1078,8 +1074,8 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
Chain};

const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
const std::optional<unsigned> Opcode = pickOpcodeForVT(
TargetVT, NVPTX::LD_i8, NVPTX::LD_i16, NVPTX::LD_i32, NVPTX::LD_i64);
const std::optional<unsigned> Opcode =
pickOpcodeForVT(TargetVT, NVPTX::LD_i16, NVPTX::LD_i32, NVPTX::LD_i64);
if (!Opcode)
return false;

Expand Down Expand Up @@ -1164,17 +1160,15 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
default:
llvm_unreachable("Unexpected opcode");
case NVPTXISD::LoadV2:
Opcode =
pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v2, NVPTX::LDV_i16_v2,
NVPTX::LDV_i32_v2, NVPTX::LDV_i64_v2);
Opcode = pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i16_v2,
NVPTX::LDV_i32_v2, NVPTX::LDV_i64_v2);
break;
case NVPTXISD::LoadV4:
Opcode =
pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i8_v4, NVPTX::LDV_i16_v4,
NVPTX::LDV_i32_v4, NVPTX::LDV_i64_v4);
Opcode = pickOpcodeForVT(EltVT.SimpleTy, NVPTX::LDV_i16_v4,
NVPTX::LDV_i32_v4, NVPTX::LDV_i64_v4);
break;
case NVPTXISD::LoadV8:
Opcode = pickOpcodeForVT(EltVT.SimpleTy, {/* no v8i8 */}, {/* no v8i16 */},
Opcode = pickOpcodeForVT(EltVT.SimpleTy, {/* no v8i16 */},
NVPTX::LDV_i32_v8, {/* no v8i64 */});
break;
}
Expand Down Expand Up @@ -1230,22 +1224,21 @@ bool NVPTXDAGToDAGISel::tryLDG(MemSDNode *LD) {
default:
llvm_unreachable("Unexpected opcode");
case ISD::LOAD:
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_i8,
NVPTX::LD_GLOBAL_NC_i16, NVPTX::LD_GLOBAL_NC_i32,
NVPTX::LD_GLOBAL_NC_i64);
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_i16,
NVPTX::LD_GLOBAL_NC_i32, NVPTX::LD_GLOBAL_NC_i64);
break;
case NVPTXISD::LoadV2:
Opcode = pickOpcodeForVT(
TargetVT, NVPTX::LD_GLOBAL_NC_v2i8, NVPTX::LD_GLOBAL_NC_v2i16,
NVPTX::LD_GLOBAL_NC_v2i32, NVPTX::LD_GLOBAL_NC_v2i64);
Opcode =
pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_v2i16,
NVPTX::LD_GLOBAL_NC_v2i32, NVPTX::LD_GLOBAL_NC_v2i64);
break;
case NVPTXISD::LoadV4:
Opcode = pickOpcodeForVT(
TargetVT, NVPTX::LD_GLOBAL_NC_v4i8, NVPTX::LD_GLOBAL_NC_v4i16,
NVPTX::LD_GLOBAL_NC_v4i32, NVPTX::LD_GLOBAL_NC_v4i64);
Opcode =
pickOpcodeForVT(TargetVT, NVPTX::LD_GLOBAL_NC_v4i16,
NVPTX::LD_GLOBAL_NC_v4i32, NVPTX::LD_GLOBAL_NC_v4i64);
break;
case NVPTXISD::LoadV8:
Opcode = pickOpcodeForVT(TargetVT, {/* no v8i8 */}, {/* no v8i16 */},
Opcode = pickOpcodeForVT(TargetVT, {/* no v8i16 */},
NVPTX::LD_GLOBAL_NC_v8i32, {/* no v8i64 */});
break;
}
Expand Down Expand Up @@ -1276,8 +1269,9 @@ bool NVPTXDAGToDAGISel::tryLDU(SDNode *N) {
break;
}

const MVT::SimpleValueType SelectVT =
MVT::getIntegerVT(LD->getMemoryVT().getSizeInBits() / NumElts).SimpleTy;
SDLoc DL(N);
const unsigned FromTypeWidth = LD->getMemoryVT().getSizeInBits() / NumElts;
const MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;

// If this is an LDU intrinsic, the address is the third operand. If its an
// LDU SD node (from custom vector handling), then its the second operand
Expand All @@ -1286,32 +1280,28 @@ bool NVPTXDAGToDAGISel::tryLDU(SDNode *N) {

SDValue Base, Offset;
SelectADDR(Addr, Base, Offset);
SDValue Ops[] = {Base, Offset, LD->getChain()};
SDValue Ops[] = {getI32Imm(FromTypeWidth, DL), Base, Offset, LD->getChain()};

std::optional<unsigned> Opcode;
switch (N->getOpcode()) {
default:
llvm_unreachable("Unexpected opcode");
case ISD::INTRINSIC_W_CHAIN:
Opcode =
pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_i8, NVPTX::LDU_GLOBAL_i16,
NVPTX::LDU_GLOBAL_i32, NVPTX::LDU_GLOBAL_i64);
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_i16,
NVPTX::LDU_GLOBAL_i32, NVPTX::LDU_GLOBAL_i64);
break;
case NVPTXISD::LDUV2:
Opcode = pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_v2i8,
NVPTX::LDU_GLOBAL_v2i16, NVPTX::LDU_GLOBAL_v2i32,
NVPTX::LDU_GLOBAL_v2i64);
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_v2i16,
NVPTX::LDU_GLOBAL_v2i32, NVPTX::LDU_GLOBAL_v2i64);
break;
case NVPTXISD::LDUV4:
Opcode = pickOpcodeForVT(SelectVT, NVPTX::LDU_GLOBAL_v4i8,
NVPTX::LDU_GLOBAL_v4i16, NVPTX::LDU_GLOBAL_v4i32,
{/* no v4i64 */});
Opcode = pickOpcodeForVT(TargetVT, NVPTX::LDU_GLOBAL_v4i16,
NVPTX::LDU_GLOBAL_v4i32, {/* no v4i64 */});
break;
}
if (!Opcode)
return false;

SDLoc DL(N);
SDNode *NVPTXLDU = CurDAG->getMachineNode(*Opcode, DL, LD->getVTList(), Ops);

ReplaceNode(LD, NVPTXLDU);
Expand Down Expand Up @@ -1362,8 +1352,8 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
Chain};

const std::optional<unsigned> Opcode =
pickOpcodeForVT(Value.getSimpleValueType().SimpleTy, NVPTX::ST_i8,
NVPTX::ST_i16, NVPTX::ST_i32, NVPTX::ST_i64);
pickOpcodeForVT(Value.getSimpleValueType().SimpleTy, NVPTX::ST_i16,
NVPTX::ST_i32, NVPTX::ST_i64);
if (!Opcode)
return false;

Expand Down Expand Up @@ -1423,16 +1413,16 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
default:
return false;
case NVPTXISD::StoreV2:
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i8_v2, NVPTX::STV_i16_v2,
NVPTX::STV_i32_v2, NVPTX::STV_i64_v2);
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i16_v2, NVPTX::STV_i32_v2,
NVPTX::STV_i64_v2);
break;
case NVPTXISD::StoreV4:
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i8_v4, NVPTX::STV_i16_v4,
NVPTX::STV_i32_v4, NVPTX::STV_i64_v4);
Opcode = pickOpcodeForVT(EltVT, NVPTX::STV_i16_v4, NVPTX::STV_i32_v4,
NVPTX::STV_i64_v4);
break;
case NVPTXISD::StoreV8:
Opcode = pickOpcodeForVT(EltVT, {/* no v8i8 */}, {/* no v8i16 */},
NVPTX::STV_i32_v8, {/* no v8i64 */});
Opcode = pickOpcodeForVT(EltVT, {/* no v8i16 */}, NVPTX::STV_i32_v8,
{/* no v8i64 */});
break;
}

Expand Down Expand Up @@ -1687,10 +1677,11 @@ bool NVPTXDAGToDAGISel::tryBF16ArithToFMA(SDNode *N) {
auto API = APF.bitcastToAPInt();
API = API.concat(API);
auto Const = CurDAG->getTargetConstant(API, DL, MVT::i32);
return SDValue(CurDAG->getMachineNode(NVPTX::IMOV32i, DL, VT, Const), 0);
return SDValue(CurDAG->getMachineNode(NVPTX::MOV_B32_i, DL, VT, Const),
0);
}
auto Const = CurDAG->getTargetConstantFP(APF, DL, VT);
return SDValue(CurDAG->getMachineNode(NVPTX::BFMOV16i, DL, VT, Const), 0);
return SDValue(CurDAG->getMachineNode(NVPTX::MOV_BF16_i, DL, VT, Const), 0);
};

switch (N->getOpcode()) {
Expand Down
10 changes: 1 addition & 9 deletions llvm/lib/Target/NVPTX/NVPTXInstrFormats.td
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Expand Up @@ -11,15 +11,9 @@
//
//===----------------------------------------------------------------------===//

// Vector instruction type enum
class VecInstTypeEnum<bits<4> val> {
bits<4> Value=val;
}
def VecNOP : VecInstTypeEnum<0>;

// Generic NVPTX Format

class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
: Instruction {
field bits<14> Inst;

Expand All @@ -30,7 +24,6 @@ class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
let Pattern = pattern;

// TSFlagFields
bits<4> VecInstType = VecNOP.Value;
bit IsLoad = false;
bit IsStore = false;

Expand All @@ -45,7 +38,6 @@ class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
// 2**(2-1) = 2.
bits<2> IsSuld = 0;

let TSFlags{3...0} = VecInstType;
let TSFlags{4} = IsLoad;
let TSFlags{5} = IsStore;
let TSFlags{6} = IsTex;
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
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Expand Up @@ -35,23 +35,23 @@ void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);

if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
if (DestRC != SrcRC)
report_fatal_error("Copy one register into another with a different width");

unsigned Op;
if (DestRC == &NVPTX::B1RegClass) {
Op = NVPTX::IMOV1r;
} else if (DestRC == &NVPTX::B16RegClass) {
Op = NVPTX::MOV16r;
} else if (DestRC == &NVPTX::B32RegClass) {
Op = NVPTX::IMOV32r;
} else if (DestRC == &NVPTX::B64RegClass) {
Op = NVPTX::IMOV64r;
} else if (DestRC == &NVPTX::B128RegClass) {
Op = NVPTX::IMOV128r;
} else {
if (DestRC == &NVPTX::B1RegClass)
Op = NVPTX::MOV_B1_r;
else if (DestRC == &NVPTX::B16RegClass)
Op = NVPTX::MOV_B16_r;
else if (DestRC == &NVPTX::B32RegClass)
Op = NVPTX::MOV_B32_r;
else if (DestRC == &NVPTX::B64RegClass)
Op = NVPTX::MOV_B64_r;
else if (DestRC == &NVPTX::B128RegClass)
Op = NVPTX::MOV_B128_r;
else
llvm_unreachable("Bad register copy");
}

BuildMI(MBB, I, DL, get(Op), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
}
Expand Down
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